timer.tan.qmsg

来自「利用一块芯片完成除时钟源、按键、扬声器和显示器（数码管）之外的所有数字电路功能。」· QMSG 代码 · 共 11 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|s2 " "Warning: Node \"contr:26\|s2\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|clkm " "Warning: Node \"contr:26\|clkm\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 6 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|s4 " "Warning: Node \"contr:26\|s4\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|clks " "Warning: Node \"contr:26\|clks\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 6 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|s0 " "Warning: Node \"contr:26\|s0\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|clkh " "Warning: Node \"contr:26\|clkh\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 6 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|clkmm " "Warning: Node \"contr:26\|clkmm\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 6 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|s5 " "Warning: Node \"contr:26\|s5\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|s3 " "Warning: Node \"contr:26\|s3\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "contr:26\|s1 " "Warning: Node \"contr:26\|s1\" is a latch" {  } { { "contr.vhd" "" { Text "F:/eda/timer/contr.vhd" 7 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "decoder:2\|q\[6\] " "Warning: Node \"decoder:2\|q\[6\]\" is a latch" {  } { { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "decoder:2\|q\[5\] " "Warning: Node \"decoder:2\|q\[5\]\" is a latch" {  } { { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "decoder:2\|q\[4\] " "Warning: Node \"decoder:2\|q\[4\]\" is a latch" {  } { { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "decoder:2\|q\[3\] " "Warning: Node \"decoder:2\|q\[3\]\" is a latch" {  } { { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "decoder:2\|q\[2\] " "Warning: Node \"decoder:2\|q\[2\]\" is a latch" {  } { { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "decoder:2\|q\[1\] " "Warning: Node \"decoder:2\|q\[1\]\" is a latch" {  } { { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "decoder:2\|q\[0\] " "Warning: Node \"decoder:2\|q\[0\]\" is a latch" {  } { { "decoder.vhd" "" { Text "F:/eda/timer/decoder.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0}