mms.rpt

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Project Information                                       f:\eda\timer\mms.rpt

MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 05/16/2007 23:16:56

Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
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under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
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programming or simulation file, or any other related documentation or
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***** Project compilation was successful


MMS


** DEVICE SUMMARY **

Chip/                     Input   Output   Bidir         Shareable
POF       Device          Pins    Pins     Pins     LCs  Expanders  % Utilized

mms       EPM7032LC44-6    2        9        0      11      0           34 %

User Pins:                 2        9        0  



Project Information                                       f:\eda\timer\mms.rpt

** PROJECT COMPILATION MESSAGES **

Warning: GLOBAL primitive on node 'clr' feeds logic -- non-global signal usage may result


Project Information                                       f:\eda\timer\mms.rpt

** AUTO GLOBAL SIGNALS **



INFO: Signal 'clr' chosen for auto global Clear


Project Information                                       f:\eda\timer\mms.rpt

** FILE HIERARCHY **



|lpm_add_sub:164|
|lpm_add_sub:164|addcore:adder|
|lpm_add_sub:164|addcore:adder|addcore:adder0|
|lpm_add_sub:164|altshift:result_ext_latency_ffs|
|lpm_add_sub:164|altshift:carry_ext_latency_ffs|
|lpm_add_sub:164|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:186|
|lpm_add_sub:186|addcore:adder|
|lpm_add_sub:186|addcore:adder|addcore:adder0|
|lpm_add_sub:186|altshift:result_ext_latency_ffs|
|lpm_add_sub:186|altshift:carry_ext_latency_ffs|
|lpm_add_sub:186|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:215|
|lpm_add_sub:215|addcore:adder|
|lpm_add_sub:215|addcore:adder|addcore:adder0|
|lpm_add_sub:215|altshift:result_ext_latency_ffs|
|lpm_add_sub:215|altshift:carry_ext_latency_ffs|
|lpm_add_sub:215|altshift:oflow_ext_latency_ffs|


Device-Specific Information:                              f:\eda\timer\mms.rpt
mms

***** Logic for device 'mms' compiled without errors.




Device: EPM7032LC44-6

Device Options:
    Turbo Bit                                    = ON
    Security Bit                                 = OFF

              R  R                             
              E  E                             
              S  S                             
              E  E                             
              R  R                       s  s  
              V  V  c  V  G  c  G  G  G  h  h  
              E  E  l  C  N  l  N  N  N  i  i  
              D  D  k  C  D  r  D  D  D  3  2  
            -----------------------------------_ 
          /   6  5  4  3  2  1 44 43 42 41 40   | 
RESERVED |  7                                39 | shi1 
RESERVED |  8                                38 | shi0 
RESERVED |  9                                37 | ge3 
     GND | 10                                36 | ge2 
RESERVED | 11                                35 | VCC 
RESERVED | 12         EPM7032LC44-6          34 | ge1 
RESERVED | 13                                33 | ge0 
RESERVED | 14                                32 | co 
     VCC | 15                                31 | RESERVED 
RESERVED | 16                                30 | GND 
RESERVED | 17                                29 | RESERVED 
         |_  18 19 20 21 22 23 24 25 26 27 28  _| 
           ------------------------------------ 
              R  R  R  R  G  V  R  R  R  R  R  
              E  E  E  E  N  C  E  E  E  E  E  
              S  S  S  S  D  C  S  S  S  S  S  
              E  E  E  E        E  E  E  E  E  
              R  R  R  R        R  R  R  R  R  
              V  V  V  V        V  V  V  V  V  
              E  E  E  E        E  E  E  E  E  
              D  D  D  D        D  D  D  D  D  


N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.



Device-Specific Information:                              f:\eda\timer\mms.rpt
mms

** RESOURCE USAGE **

                                                Shareable     External
Logic Array Block     Logic Cells   I/O Pins    Expanders   Interconnect

A:     LC1 - LC16     0/16(  0%)   1/16(  6%)   0/16(  0%)   0/36(  0%) 
B:    LC17 - LC32    11/16( 68%)   9/16( 56%)   1/16(  6%)  12/36( 33%) 


Total dedicated input pins used:                 1/4      ( 25%)
Total I/O pins used:                            10/32     ( 31%)
Total logic cells used:                         11/32     ( 34%)
Total shareable expanders used:                  0/32     (  0%)
Total Turbo logic cells used:                   11/32     ( 34%)
Total shareable expanders not available (n/a):   1/32     (  3%)
Average fan-in:                                  7.36
Total fan-in:                                    81

Total input pins required:                       2
Total output pins required:                      9
Total bidirectional pins required:               0
Total logic cells required:                     11
Total flipflops required:                        9
Total product terms required:                   31
Total logic cells lending parallel expanders:    0
Total shareable expanders in database:           0

Synthesized logic cells:                         0/  32   (  0%)



Device-Specific Information:                              f:\eda\timer\mms.rpt
mms

** INPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
   4    (1)  (A)      INPUT               0      0   0    0    0    9    0  clk
   1      -   -       INPUT  G            0      0   0    0    0    1    0  clr


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.


Device-Specific Information:                              f:\eda\timer\mms.rpt
mms

** OUTPUTS **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
  32     25    B         FF      t        0      0   0    2    8    0    0  co
  33     24    B         FF      t        0      0   0    1    0    8    2  ge0
  34     23    B         FF      t        0      0   0    1    4    8    2  ge1
  36     22    B         FF      t        0      0   0    1    2    7    2  ge2
  37     21    B         FF      t        1      0   1    1   10    7    2  ge3
  38     20    B         FF      t        0      0   0    1    4    5    0  shi0
  39     19    B         FF      t        0      0   0    1    8    5    0  shi1
  40     18    B         FF      t        0      0   0    1    6    4    0  shi2
  41     17    B         FF      t        0      0   0    1    8    4    0  shi3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                              f:\eda\timer\mms.rpt
mms