mms.rpt

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** BURIED LOGIC **

                                         Shareable
                                         Expanders     Fan-In    Fan-Out
 Pin     LC  LAB  Primitive    Code   Total Shared n/a INP  FBK  OUT  FBK  Name
 (31)    26    B       SOFT      t        0      0   0    0    4    1    0  |LPM_ADD_SUB:164|addcore:adder|addcore:adder0|result_node3
 (29)    27    B       SOFT      t        0      0   0    0    4    1    0  |LPM_ADD_SUB:215|addcore:adder|addcore:adder0|result_node3


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                              f:\eda\timer\mms.rpt
mms

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                               Logic cells placed in LAB 'B'
        +--------------------- LC25 co
        | +------------------- LC24 ge0
        | | +----------------- LC23 ge1
        | | | +--------------- LC22 ge2
        | | | | +------------- LC21 ge3
        | | | | | +----------- LC26 |LPM_ADD_SUB:164|addcore:adder|addcore:adder0|result_node3
        | | | | | | +--------- LC27 |LPM_ADD_SUB:215|addcore:adder|addcore:adder0|result_node3
        | | | | | | | +------- LC20 shi0
        | | | | | | | | +----- LC19 shi1
        | | | | | | | | | +--- LC18 shi2
        | | | | | | | | | | +- LC17 shi3
        | | | | | | | | | | | 
        | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC24 -> * * * * * * * * * * * | - * | <-- ge0
LC23 -> * - * * * * * * * * * | - * | <-- ge1
LC22 -> * - * * * * * * * * * | - * | <-- ge2
LC21 -> * - * - * * * * * * * | - * | <-- ge3
LC26 -> - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:164|addcore:adder|addcore:adder0|result_node3
LC27 -> - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:215|addcore:adder|addcore:adder0|result_node3
LC20 -> * - - - * - - * * * * | - * | <-- shi0
LC19 -> * - - - * - - - * * * | - * | <-- shi1
LC18 -> * - - - * - - - * * * | - * | <-- shi2
LC17 -> * - - - * - - - * - * | - * | <-- shi3

Pin
4    -> * * * * * - - * * * * | - * | <-- clk
1    -> * - - - - - - - - - - | - * | <-- clr


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                              f:\eda\timer\mms.rpt
mms

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;

-- Node name is 'co' = ':3' 
-- Equation name is 'co', type is output 
 co      = TFFE( _EQ001, !clk,  VCC,  VCC,  VCC);
  _EQ001 =  clr &  ge0 & !ge1 &  ge2 & !ge3 &  shi0 & !shi1 &  shi2 & !shi3
         #  clr &  ge0 & !ge1 & !ge2 &  ge3 &  shi0 & !shi1 & !shi2 &  shi3;

-- Node name is 'ge0' = ':11' 
-- Equation name is 'ge0', type is output 
 ge0     = TFFE( VCC, !clk, GLOBAL( clr),  VCC,  VCC);

-- Node name is 'ge1' = ':9' 
-- Equation name is 'ge1', type is output 
 ge1     = DFFE( _EQ002 $  VCC, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ002 =  ge0 & !ge1 & !ge2 &  ge3
         #  ge0 &  ge1
         # !ge0 & !ge1;

-- Node name is 'ge2' = ':7' 
-- Equation name is 'ge2', type is output 
 ge2     = TFFE( _EQ003, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ003 =  ge0 &  ge1;

-- Node name is 'ge3' = ':5' 
-- Equation name is 'ge3', type is output 
 ge3     = DFFE( _EQ004 $  _LC027, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ004 =  ge0 & !ge1 &  ge2 & !ge3 &  _LC026 & !_LC027 &  shi0 & !shi1 & 
              shi2 & !shi3
         #  ge0 & !ge1 &  ge2 & !ge3 & !_LC026 &  _LC027 &  shi0 & !shi1 & 
              shi2 & !shi3
         #  ge0 & !ge1 & !ge2 &  ge3 &  _LC027;

-- Node name is 'shi0' = ':19' 
-- Equation name is 'shi0', type is output 
 shi0    = TFFE( _EQ005, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ005 =  ge0 & !ge1 & !ge2 &  ge3;

-- Node name is 'shi1' = ':17' 
-- Equation name is 'shi1', type is output 
 shi1    = TFFE( _EQ006, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ006 =  ge0 & !ge1 & !ge2 &  ge3 &  shi0 & !shi1 &  shi2
         #  ge0 & !ge1 & !ge2 &  ge3 &  shi0 & !shi1 & !shi3
         #  ge0 & !ge1 & !ge2 &  ge3 &  shi0 &  shi1;

-- Node name is 'shi2' = ':15' 
-- Equation name is 'shi2', type is output 
 shi2    = TFFE( _EQ007, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ007 =  ge0 & !ge1 & !ge2 &  ge3 &  shi0 &  shi1;

-- Node name is 'shi3' = ':13' 
-- Equation name is 'shi3', type is output 
 shi3    = TFFE( _EQ008, !clk, GLOBAL( clr),  VCC,  VCC);
  _EQ008 =  ge0 & !ge1 & !ge2 &  ge3 &  shi0 & !shi1 & !shi2 &  shi3
         #  ge0 & !ge1 & !ge2 &  ge3 &  shi0 &  shi1 &  shi2;

-- Node name is '|LPM_ADD_SUB:164|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC026', type is buried 
_LC026   = LCELL( ge3 $  _EQ009);
  _EQ009 =  ge0 &  ge1 &  ge2;

-- Node name is '|LPM_ADD_SUB:215|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC027', type is buried 
_LC027   = LCELL( ge3 $  _EQ010);
  _EQ010 =  ge0 &  ge1 &  ge2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                       f:\eda\timer\mms.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,845K