📄 hour.rpt
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Project Information e:\kai\timer\hour.rpt
MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 05/16/2007 20:57:19
Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
HOUR
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
hour EPM7032LC44-6 4 9 0 14 15 43 %
User Pins: 4 9 0
Project Information e:\kai\timer\hour.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clr' chosen for auto global Clear
Project Information e:\kai\timer\hour.rpt
** FILE HIERARCHY **
|lpm_add_sub:185|
|lpm_add_sub:185|addcore:adder|
|lpm_add_sub:185|addcore:adder|addcore:adder0|
|lpm_add_sub:185|altshift:result_ext_latency_ffs|
|lpm_add_sub:185|altshift:carry_ext_latency_ffs|
|lpm_add_sub:185|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:262|
|lpm_add_sub:262|addcore:adder|
|lpm_add_sub:262|addcore:adder|addcore:adder0|
|lpm_add_sub:262|altshift:result_ext_latency_ffs|
|lpm_add_sub:262|altshift:carry_ext_latency_ffs|
|lpm_add_sub:262|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:336|
|lpm_add_sub:336|addcore:adder|
|lpm_add_sub:336|addcore:adder|addcore:adder0|
|lpm_add_sub:336|altshift:result_ext_latency_ffs|
|lpm_add_sub:336|altshift:carry_ext_latency_ffs|
|lpm_add_sub:336|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:358|
|lpm_add_sub:358|addcore:adder|
|lpm_add_sub:358|addcore:adder|addcore:adder0|
|lpm_add_sub:358|altshift:result_ext_latency_ffs|
|lpm_add_sub:358|altshift:carry_ext_latency_ffs|
|lpm_add_sub:358|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:387|
|lpm_add_sub:387|addcore:adder|
|lpm_add_sub:387|addcore:adder|addcore:adder0|
|lpm_add_sub:387|altshift:result_ext_latency_ffs|
|lpm_add_sub:387|altshift:carry_ext_latency_ffs|
|lpm_add_sub:387|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\kai\timer\hour.rpt
hour
***** Logic for device 'hour' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
s s s
e e c V G c G G G g h
t t l C N l N N N e i
1 0 k C D r D D D 3 0
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
RESERVED | 7 39 | ge2
RESERVED | 8 38 | shi1
RESERVED | 9 37 | ge1
GND | 10 36 | shi2
RESERVED | 11 35 | VCC
RESERVED | 12 EPM7032LC44-6 34 | ge0
RESERVED | 13 33 | shi3
RESERVED | 14 32 | co
VCC | 15 31 | RESERVED
RESERVED | 16 30 | GND
RESERVED | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V R R R R R
E E E E N C E E E E E
S S S S D C S S S S S
E E E E E E E E E
R R R R R R R R R
V V V V V V V V V
E E E E E E E E E
D D D D D D D D D
N.C. = No Connect, This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\kai\timer\hour.rpt
hour
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 0/16( 0%) 3/16( 18%) 0/16( 0%) 0/36( 0%)
B: LC17 - LC32 14/16( 87%) 9/16( 56%) 16/16(100%) 17/36( 47%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 12/32 ( 37%)
Total logic cells used: 14/32 ( 43%)
Total shareable expanders used: 15/32 ( 46%)
Total Turbo logic cells used: 14/32 ( 43%)
Total shareable expanders not available (n/a): 1/32 ( 3%)
Average fan-in: 8.64
Total fan-in: 121
Total input pins required: 4
Total output pins required: 9
Total bidirectional pins required: 0
Total logic cells required: 14
Total flipflops required: 9
Total product terms required: 57
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 15
Synthesized logic cells: 0/ 32 ( 0%)
Device-Specific Information: e:\kai\timer\hour.rpt
hour
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 9 0 clk
1 - - INPUT G 0 0 0 0 0 0 0 clr
5 (2) (A) INPUT 0 0 0 0 0 8 0 set0
6 (3) (A) INPUT 0 0 0 0 0 9 0 set1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\kai\timer\hour.rpt
hour
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
32 25 B FF t 0 0 0 3 9 1 0 co
34 23 B FF t 0 0 0 3 8 9 3 ge0
37 21 B FF t 0 0 0 2 4 9 3 ge1
39 19 B FF t 0 0 0 3 8 9 3 ge2
41 17 B FF t 11 0 1 3 11 9 3 ge3
40 18 B FF t 0 0 0 3 4 7 2 shi0
38 20 B FF t 4 0 0 3 10 7 2 shi1
36 22 B FF t 0 0 0 3 6 6 0 shi2
33 24 B FF t 1 0 0 3 8 6 0 shi3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\kai\timer\hour.rpt
hour
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(24) 32 B SOFT t 0 0 0 0 2 1 0 |LPM_ADD_SUB:185|addcore:adder|addcore:adder0|result_node1
(25) 31 B SOFT t 0 0 0 0 4 1 0 |LPM_ADD_SUB:262|addcore:adder|addcore:adder0|result_node3
(26) 30 B SOFT t 0 0 0 0 4 1 0 |LPM_ADD_SUB:336|addcore:adder|addcore:adder0|result_node3
(27) 29 B SOFT t 0 0 0 0 2 1 0 |LPM_ADD_SUB:358|addcore:adder|addcore:adder0|result_node1
(29) 27 B SOFT t 0 0 0 0 4 1 0 |LPM_ADD_SUB:387|addcore:adder|addcore:adder0|result_node3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\kai\timer\hour.rpt
hour
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+--------------------------- LC25 co
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