test_afifo_2.v

异步fifo的verilog程序

//FILE NAME: test_afifo_2
//AUTHOR:    jialiang

`timescale 1ns/1ns

module test_afifo;
       
  parameter    DATA_WIDTH    = 8;
  parameter    ADDRESS_WIDTH = 6;
  parameter    FIFO_DEPTH    = 64;
    
  reg   clk_read, clk_write, rst;
  reg   read, write;
  reg   [DATA_WIDTH-1:0] data_in;
  wire  full,empty;
  wire  [DATA_WIDTH-1:0] data_out;

  initial #10000 $stop;
  initial begin
       rst =0; 
       #50 rst = 1;
   end
 
  initial begin  
       clk_read = 0;  
       forever #20 clk_read = ~clk_read; 
  end //25MHz

  initial begin  
       clk_write = 0;  
       forever #8  clk_write = ~clk_write; 
  end//60MHz

  initial begin     
       read =0 ;
       write =0;
       data_in = 0;
   end

  always begin
        #7    write   <= $random;
        #17   read    <= $random;
  end  
    
  always @ (posedge clk_write or negedge rst)begin
    if (!rst) begin
        data_in <= 0;
    end
    else  begin
       if (!full&write) begin
           data_in <= data_in + 1;
       end
    end
  end //always @ (posedge clk_write or negedge rst)

  /*initial begin
      repeat (50)    #40 read = ~read;
      #40 repeat (100) #30 read = ~read;
      #50 read = 1;
  end

  initial begin
      #50 write = 1;
      #2000 write = 0;
      repeat (100)    #40 write = ~write;
  end*/
   
  aFifo_2 fifo(
               data_out, empty,full,
               data_in,clk_read,read,
               clk_write,write,rst
               );

endmodule