shifter.vhd

VHDL实现循环码编码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity shifter is
	port
	(	clk    :in  std_logic;
		en	:in  std_logic;
		clear	:in  std_logic;
		input  :in  std_logic;
		output :out std_logic);
end shifter;

architecture behave_shifter of shifter is
	signal tmp :std_logic;
begin
	process(clk)
	begin
		if(clk'event and clk='1') then
			if(clear='1') then
				tmp <= '0';
				output <= '0';
			elsif(en='1') then
				output <=tmp;
				tmp <= input;
			else
				output <=tmp;
			end if;
		end if;
	end process;
end behave_shifter;