encoder.vhd

VHDL实现循环码编码

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity encoder is
	port
	(	clki	:in  std_logic;
		start	:in  std_logic;
		reset	:in  std_logic;
		aa,bb		:out std_logic;
		i   	:in  std_logic_vector(3 downto 0);
		o   	:out std_logic_vector(6 downto 0)
		);
end encoder;

architecture behave_encoder of encoder is
	component shifter is
		port(	clk		:in  std_logic;
				en		:in  std_logic;
				clear	:in  std_logic;
				input	:in  std_logic;
				output	:out std_logic);
	end component;
	component switch is
		port(	ch		:in  std_logic;
				i1		:in  std_logic;
				i2		:in  std_logic;
				o1		:out std_logic;
				o2		:out std_logic);
	end component;
	signal    enable,cleari,choose	: std_logic;
	signal    a,b,t0,t1,t2,t3,t4,t5	: std_logic;
	signal    count					: std_logic_vector(3 downto 0);
begin
	process(clki)
	begin

		if(clki'event and clki ='1') then
			if(reset ='1') then
					enable<='0';
					count<="0000";
					cleari<='1';
			elsif(start='1') then
				case count is
				when "0000" =>
					cleari<='0';
					t0<=i(3);
					enable<='1';
					choose<='0';
					count<="0001";
				when "0001" =>
					o(6)<=t5;
					enable<='0';
					count<="0010";
				when "0010" =>
					t0<=i(2);
					enable<='1';
					count<="0011";
				when "0011" =>
					o(5)<=t5;
					enable<='0';
					count<="0100";
				when "0100" =>
					t0<=i(1);
					enable<='1';
					count<="0101";
				when "0101" =>
					o(4)<=t5;
					enable<='0';
					count<="0110";
				when "0110" =>
					t0<=i(0);
					enable<='1';
					count<="0111";
				when "0111" =>
					o(3)<=t5;
					enable<='0';
					choose<='1';
					count<="1000";
				when "1000" =>
					t0<='0';
					enable<='1';
					count<="1001";
				when "1001" =>
					o(2)<=t5;
					enable<='0';
					count<="1010";
				when "1010" =>
					t0<='0';
					enable<='1';
					count<="1011";
				when "1011" =>
					o(1)<=t5;
					enable<='0';
					count<="1100";
				when "1100" =>
					t0<='0';
					enable<='1';
					count<="1101";
				when "1101" =>
					o(0)<=t5;
					enable<='0';
					count<="1110";
				when others=>
					NULL;

				end case;
			end if;
		end if;
	end process;
	aa<=a;bb<=b;
	sw	: switch  port map(ch=>choose,i1=>t0,i2=>t4,o1=>a,o2=>b);
	sh1 : shifter port map(clk=>clki,en=>enable,clear=>cleari,input=>a,output=>t1);
	sh2 : shifter port map(clk=>clki,en=>enable,clear=>cleari,input=>t2,output=>t3);
	sh3 : shifter port map(clk=>clki,en=>enable,clear=>cleari,input=>t3,output=>t4);
	t2 <=t1 XOR a;
	t5 <=t0 OR b;
end behave_encoder;