uni_dir_bus.v.doc

VerilogHDL_advanced_digital_design_code_Ch6 Verilog HDL 高级数字设计源码ch6

vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|12 Jun 2002 17:38:30 -0000
vti_extenderversion:SR|5.0.2.4330
vti_author:SR|EAS\\ciletti
vti_modifiedby:SR|EAS\\ciletti
vti_timecreated:TR|12 Jun 2002 17:38:30 -0000
vti_cacheddtm:TX|12 Jun 2002 17:38:30 -0000
vti_filesize:IR|19456
vti_cachedtitle:SR|module Uni_dir_bus ( data_to_bus, bus_enable);
vti_title:SR|module Uni_dir_bus ( data_to_bus, bus_enable);
vti_assignedto:SR|
vti_approvallevel:SR|
_PID_GUID:SW|
vti_cachedcustomprops:VX|_PID_GUID
vti_lineageid:SR|{68BF5562-B4CC-4443-B257-C158DE00D25A}
vti_backlinkinfo:VX|