mem_ctrl.v

xilinx公司的ＤＤＲ实现源码

	                     if(auto_ref_r)
			        next_state = PRECHARGE;
	                     else if (conflict_detect)
				      next_state = COMMAND_WAIT_CONF;
	                     else if (WR)
			       next_state = BURST_WRITE;
	                     else if(RD)
			       next_state = BURST_READ;
	                   end
	                     
	                  
     
     BURST_WRITE        :  next_state = WRITE_WAIT;
     
     WRITE_WAIT          : begin
        if ((conflict_detect & (~conflict_resolved_r))|| auto_ref_r)  begin	   
             next_state = WRITE_BANK_CONF;	     
	end else if ((WR) && (wrburst_cnt_r < 3'b010)) begin
           next_state = BURST_WRITE;
        end else if ((WR) && (wrburst_cnt_r == 3'b010)) begin
           next_state = BURST_WRITE;
	   burst_write = 1'd1;
        end else if ((wrburst_cnt_r <= 3'b010) && (wr_to_rd_count_r <= 4'd1))begin
           next_state = COMMAND_WAIT;
        end
     end // case: WRITE_WAIT
                            
 
     BURST_READ : next_state = READ_WAIT;
     
 
READ_WAIT          : begin
        if ((conflict_detect & (~conflict_resolved_r)) || auto_ref_r) begin
             next_state = READ_BANK_CONF;  
        end else if ((RD) && (read_burst_cnt_r == 3'b010)) begin
           next_state = BURST_READ;
	   burst_read = 1'd1;
	end else if ((RD) && (read_burst_cnt_r < 3'b010)) begin
           next_state = BURST_READ;
        end else if ((read_burst_cnt_r <= 3'b010) && (rd_to_wr_count_r <= 4'd1))  begin
           next_state = COMMAND_WAIT;  
        end
     end // case: READ_WAIT


WRITE_BANK_CONF: begin
            if(auto_ref_r)
	      next_state = PRECHARGE;
            else if(bank_conf_r)begin
	      if(no_precharge_r)
		next_state = ACTIVE;
	      else if ((wtp_count_r == 4'b0000) && (ras_count_r == 4'b0000))
		next_state = PRECHARGE;
	    end else if ((WR) && (wrburst_cnt_r < 3'b010)) begin
                next_state = BURST_WRITE;
            end else if ((WR) && (wrburst_cnt_r == 3'b010)) begin
                next_state = BURST_WRITE;
	        burst_write = 1'd1;
            end else if ((wrburst_cnt_r <= 3'b010) && (wr_to_rd_count_r <= 4'd1))begin
                next_state = COMMAND_WAIT;
            end
end // case: BANK_WRITE_CONF


READ_BANK_CONF: begin
                 if(auto_ref_r)
	             next_state = PRECHARGE;
                 else if(bank_conf_r)begin
	            if(no_precharge_r)
		      next_state = ACTIVE;
	            else if ((rtp_count_r == 4'b0000) && (ras_count_r == 4'b0000))
		      next_state = PRECHARGE;
	          end else if ((RD) && (read_burst_cnt_r == 3'b010)) begin
                      next_state = BURST_READ;
	              burst_read = 1'd1;
	          end else if ((RD) && (read_burst_cnt_r < 3'b010)) begin
                      next_state = BURST_READ;
                   end else if ((read_burst_cnt_r <= 3'b010) && (rd_to_wr_count_r <= 4'd1))  begin
                      next_state = COMMAND_WAIT;  
               end
end // case: READ_BANK_CONF

COMMAND_WAIT_CONF:begin
		    if(bank_conf_r) begin
		      if(no_precharge_r)
			next_state = ACTIVE;
		      else 
		        next_state = PRECHARGE;
		    end  else if (WR)
		      next_state = BURST_WRITE;
	            else if(RD)
		      next_state = BURST_READ;
		    else
		       next_state = COMMAND_WAIT;
                   end
		      
		  
     
   endcase // case(state)
end // always @ (...

      
//register command outputs
always @ (posedge clk0) begin
   if (rst) begin
      state_r1 <= 5'b00000;
      state_r2 <= 5'b00000;
      burst_read_r <= 1'd0;
      burst_write_r <= 1'd0;
      burst_read_r1 <= 1'd0;
      burst_read_r2 <= 1'd0;
   end else begin
      state_r1 <= state_r;
      state_r2 <= state_r1;
      burst_read_r <= burst_read;
      burst_write_r <= burst_write;
      burst_read_r1 <= burst_read_r;
      burst_read_r2 <= burst_read_r1;
   end
end

// commands to the memory
always @ (posedge clk0) begin
   if (rst)
      ddr2_ras_r <= 1'b1;
   else if (state_r == AUTO_REFRESH || state_r == ACTIVE || state_r == PRECHARGE)
      ddr2_ras_r <= 1'b0;
   else ddr2_ras_r <= 1'b1;
end

// commands to the memory
always @ (posedge clk0) begin
   if (rst)
      ddr2_cas_r <= 1'b1;
   else if (state_r == BURST_WRITE || state_r == BURST_READ || state_r == AUTO_REFRESH)
      ddr2_cas_r <= 1'b0;
   else
      ddr2_cas_r <= 1'b1;
end // always @ (posedge clk0)

// commands to the memory
always @ (posedge clk0) begin
   if (rst)
      ddr2_we_r <= 1'b1;
   else if (state_r == BURST_WRITE || state_r == PRECHARGE )
      ddr2_we_r <= 1'b0;
   else ddr2_we_r <= 1'b1;
end

//register commands to the memory
always @ (posedge clk0) begin
   if (rst) begin
      ddr2_ras_r1 <= 1'b1;
      ddr2_cas_r1 <= 1'b1;
      ddr2_we_r1 <= 1'b1;
   end else begin
      ddr2_ras_r1  <= ddr2_ras_r; 
      ddr2_cas_r1  <= ddr2_cas_r;
      ddr2_we_r1   <= ddr2_we_r;
  end
end

always @ (posedge clk0) begin
  if (rst) begin
       row_addr_r[`row_address-1:0] <= `row_address'h0000;
  end else
       row_addr_r[`row_address-1:0] <= af_addr[`row_range_end:`row_range_start];

end


// chip enable generation logic

always@(posedge clk0)
begin
   if (rst)  begin
      ddr2_cs_r[`cs_width-1 : 0] <=  `cs_width'h0;
   end else begin
      if (af_addr_r[`cs_range_end:`cs_range_start]  ==  `chip_address'h0) begin
         ddr2_cs_r[`cs_width-1 : 0] <= `cs_width'hE; 
      end  else if (af_addr_r[`cs_range_end:`cs_range_start] == `chip_address'h1) begin
         ddr2_cs_r[`cs_width-1 : 0] <= `cs_width'hD;  
      end else if (af_addr_r[`cs_range_end:`cs_range_start] == `chip_address'h2) begin
         ddr2_cs_r[`cs_width-1 : 0] <= `cs_width'hB; 
      end else if (af_addr_r[`cs_range_end:`cs_range_start] == `chip_address'h3) begin
         ddr2_cs_r[`cs_width-1 : 0] <= `cs_width'h7; 
      end else
        ddr2_cs_r[`cs_width-1 : 0] <= `cs_width'hF;  
   end // else: !if(rst)
end // always@ (posedge clk0)


always @ (posedge clk0) begin
   if (rst) begin
      ddr2_address_r <= `row_address'h0000;
   end else if ((state_r1 == ACTIVE)) begin // if (init_memory)
      ddr2_address_r <= row_addr_r;        
   end else if (state_r1 == BURST_WRITE || state_r1 == BURST_READ) begin
      ddr2_address_r <= {zeroes[(`row_address - (`column_address+1))-1:0 ], af_addr_r1[`col_range_end:`col_range_start]};
   end else if ((state_r1 == PRECHARGE) && auto_ref_r) begin
        ddr2_address_r <= `row_address'h0400;
   end else ddr2_address_r <= `row_address'h0000;
end // always @ (posedge clk0)

   
always @ (posedge clk0) begin
   if (rst) begin
      ddr2_ba_r[`bank_address-1:0] <= `bank_address'h0;
   end else if (state_r1 == PRECHARGE) begin
       if(bank_conf_r && ~bank_hit_r)
           ddr2_ba_r[`bank_address-1:0] <= precharge_bank_r;
       else
           ddr2_ba_r[`bank_address-1:0] <= af_addr_r1[`bank_range_end:`bank_range_start];       
   end else if((state_r1 == BURST_WRITE) || (state_r1 == BURST_READ) || (state_r1 == ACTIVE))
           ddr2_ba_r[`bank_address-1:0] <= af_addr_r1[`bank_range_end:`bank_range_start];
end // always @ (posedge clk0)

always @ (posedge clk0) begin
   if (rst) begin
      ddr2_cs_r1[`cs_width-1:0] <= `cs_width'h0;  
   end else if ((state_r1 == AUTO_REFRESH )) begin
      if (auto_cnt_r == 3'h1) begin
         ddr2_cs_r1[`cs_width-1:0] <= `cs_width'hE; 
      end else if (auto_cnt_r == 3'h2) begin
         ddr2_cs_r1[`cs_width-1:0] <= `cs_width'hD; 
      end else if (auto_cnt_r == 3'h3) begin
         ddr2_cs_r1[`cs_width-1:0] <= `cs_width'hB; 
      end else if (auto_cnt_r == 3'h4) begin
         ddr2_cs_r1[`cs_width-1:0] <= `cs_width'h7; 
      end else
        ddr2_cs_r1[`cs_width-1:0] <= `cs_width'hF;              	
   end else if ((state_r1 == ACTIVE )||(state_r1 == PRECHARGE_WAIT ))  begin
   
      ddr2_cs_r1[`cs_width-1:0] <= ddr2_cs_r[`cs_width-1:0];
   end else
     ddr2_cs_r1[`cs_width-1:0] <= ddr2_cs_r1[`cs_width-1:0];
   
end // always @ (posedge clk0)


always @ (posedge clk0) begin
   if (rst) begin
      conflict_resolved_r <= 1'b0;
   end else begin
     // if ((state_r == PRECHARGE_WAIT) & conflict_detect_r)
        if(state_r == ACTIVE)
        conflict_resolved_r  <= 1'b1;
      else if(af_rden)
        conflict_resolved_r  <= 1'b0;
   end
end



// odt

always @ (posedge clk0) begin
   if (rst)
     odt_en_cnt_r <= 4'b0000;
   else if(((state_r == BURST_WRITE) && ~burst_write_r)&& odt_enable)
     odt_en_cnt_r <= ((add_lat + cas_lat  )-2);
   else if(((state_r == BURST_READ) && ~burst_read_r)&& odt_enable)
     odt_en_cnt_r <= ((add_lat + cas_lat )-1);
   else if(odt_en_cnt_r != 4'b0000)
     odt_en_cnt_r <= odt_en_cnt_r - 1'b1;
    else 
     odt_en_cnt_r <= 4'b0000;
end

always @ (posedge clk0) begin
   if (rst)
     odt_cnt_r <= 4'b0000;
   else if((state_r == BURST_WRITE) )
     odt_cnt_r <= ((add_lat + cas_lat + burst_cnt));
   else if((state_r == BURST_READ) )
     odt_cnt_r <= ((add_lat + cas_lat + burst_cnt+1));
   else if(odt_cnt_r != 4'b0000)
     odt_cnt_r <= odt_cnt_r - 1'b1;
   else  
     odt_cnt_r <= 4'b0000;
   
end



always @ (posedge clk0) begin
   if (rst)
     odt_en  <= `cs_width'h0;
   else if((odt_en_cnt_r == 4'b0001))
     odt_en  <= `cs_width'hF;
   else if (odt_cnt_r == 4'b0010)
     odt_en <= `cs_width'h0;
end


always @ (posedge clk0) begin
   if (rst) 
	ddr2_cs_r2  <= `cs_width'h0;
    else 
	ddr2_cs_r2   <= ddr2_cs_r1;
	
end

always @ (odt_en or  ddr2_cs_r2)begin
      	ctrl_odt  = `cs_width'h0;
   if ( `cs_width == 1 ) begin
       if (ddr2_cs_r2[`cs_width-1 : 0]==`cs_width'h0) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 1);
       else
           ctrl_odt = `cs_width'h0;
           
   end else if ( `cs_width == 2 ) begin
       if (ddr2_cs_r2[`cs_width-1 : 0]  ==  `cs_width'h2) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 10);
       else if (ddr2_cs_r2[`cs_width-1 : 0]  ==  `cs_width'h1) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 01);
       else
         ctrl_odt = `cs_width'h0; 
         
    end  else if ( `cs_width == 3 )  begin
       if (ddr2_cs_r2[`cs_width-1 : 0]  ==  `cs_width'h6) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 100);
       else if (ddr2_cs_r2[`cs_width-1 : 0]  ==  `cs_width'h5) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 100);
       else if (ddr2_cs_r2[`cs_width-1 : 0]  ==  `cs_width'h3) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 010);
       else
         ctrl_odt = `cs_width'h0;
         
   end  else if ( `cs_width == 4 )  begin
       if (ddr2_cs_r2[`cs_width-1 : 0]  ==  `cs_width'hE) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 1000);
       else if (ddr2_cs_r2[`cs_width-1 : 0]  ==  `cs_width'hD) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 1000);
       else if (ddr2_cs_r2[`cs_width-1 : 0]  == `cs_width'hB) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 1000);
       else if (ddr2_cs_r2[`cs_width-1 : 0]  ==  `cs_width'h7) 
           ctrl_odt = (odt_en[`cs_width-1 : 0] & 0100);
       else
         ctrl_odt = `cs_width'h0; 
    end 
end

assign ctrl_address[`row_address-1:0]  = ddr2_address_r[`row_address-1:0];
assign ctrl_ba [`bank_address-1:0]     = ddr2_ba_r[`bank_address-1:0];     
assign ctrl_ras_n = ddr2_ras_r1;  
assign ctrl_cas_n = ddr2_cas_r1;  
assign ctrl_we_n  = ddr2_we_r1;   
//assign ctrl_odt  = ctrl_odt; 
//assign ctrl_cs_n = ddr2_cs_r1;

   assign ctrl_cs_n = 2'd0;
  


endmodule // ddr2_controller_0