timesim.vhd

以太网16B/20B源代码包括编码器和解码器功能

  signal upper_enc_s_func_prs_state_FFD2_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD2_MC_D2 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT1_MC_Q : STD_LOGIC; 
  signal lower_enc_prs_state_FFT1_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_prs_state_FFT1_MC_D : STD_LOGIC; 
  signal lower_enc_prs_state_FFT1_MC_D1 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT1_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT1_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT1_MC_D2 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT1_MC_D_TFF : STD_LOGIC; 
  signal lower_enc_prs_state_FFT2_MC_Q : STD_LOGIC; 
  signal lower_enc_prs_state_FFT2_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_prs_state_FFT2_MC_D : STD_LOGIC; 
  signal lower_enc_prs_state_FFT2_MC_D1 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT2_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT2 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT2_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT2_MC_D2 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT2_MC_D_TFF : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3_MC_Q : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3_MC_D1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT3_MC_D_TFF : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1_MC_Q : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1_MC_D1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD1 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT1_MC_D_TFF : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT2_MC_Q : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT2_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT2_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT2_MC_D1_PT_0 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT2_MC_D1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT2_MC_D2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_prs_state_FFT2_MC_D_TFF : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD1_MC_Q : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD1_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD1_MC_D : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD1_MC_D1 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD1_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD1_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD1_MC_D2 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD2_MC_Q : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD2_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD2_MC_D : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD2_MC_D1 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD2_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD2_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD2_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_s_func_prs_state_FFD2_MC_D2 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_Q : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D1 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_9 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_10 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_11 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_12 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_13 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_14 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_15 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2_PT_16 : STD_LOGIC; 
  signal lower_enc_dis_func_N132_MC_D2 : STD_LOGIC; 
  signal N_PZ_1737_MC_Q : STD_LOGIC; 
  signal N_PZ_1737_MC_D : STD_LOGIC; 
  signal N_PZ_1737_MC_D1_PT_0 : STD_LOGIC; 
  signal N_PZ_1737_MC_D1 : STD_LOGIC; 
  signal N_PZ_1737_MC_D2 : STD_LOGIC; 
  signal lower_enc_N168_MC_Q : STD_LOGIC; 
  signal lower_enc_N168_MC_D : STD_LOGIC; 
  signal lower_enc_N168_MC_D1 : STD_LOGIC; 
  signal data_trs_5_II_UIM : STD_LOGIC; 
  signal lower_enc_N168_MC_D2_PT_0 : STD_LOGIC; 
  signal data_trs_6_II_UIM : STD_LOGIC; 
  signal lower_enc_N168_MC_D2_PT_1 : STD_LOGIC; 
  signal data_trs_7_II_UIM : STD_LOGIC; 
  signal lower_enc_N168_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_N168_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_N168_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_enc_N168_MC_D2 : STD_LOGIC; 
  signal N_PZ_330_MC_Q : STD_LOGIC; 
  signal N_PZ_330_MC_D : STD_LOGIC; 
  signal N_PZ_330_MC_D1 : STD_LOGIC; 
  signal N_PZ_330_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_330_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_330_MC_D2 : STD_LOGIC; 
  signal N99_MC_Q : STD_LOGIC; 
  signal N99_MC_D : STD_LOGIC; 
  signal dis_in_II_UIM : STD_LOGIC; 
  signal N99_MC_D1_PT_0 : STD_LOGIC; 
  signal N99_MC_D1 : STD_LOGIC; 
  signal N99_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_N162 : STD_LOGIC; 
  signal upper_enc_dis_func_N174 : STD_LOGIC; 
  signal N99_MC_D2_PT_1 : STD_LOGIC; 
  signal data_trs_13_II_UIM : STD_LOGIC; 
  signal data_trs_14_II_UIM : STD_LOGIC; 
  signal N99_MC_D2_PT_2 : STD_LOGIC; 
  signal N99_MC_D2_PT_3 : STD_LOGIC; 
  signal data_trs_15_II_UIM : STD_LOGIC; 
  signal N99_MC_D2_PT_4 : STD_LOGIC; 
  signal N_PZ_328 : STD_LOGIC; 
  signal N99_MC_D2_PT_5 : STD_LOGIC; 
  signal N99_MC_D2_PT_6 : STD_LOGIC; 
  signal N99_MC_D2_PT_7 : STD_LOGIC; 
  signal N99_MC_D2_PT_8 : STD_LOGIC; 
  signal N99_MC_D2_PT_9 : STD_LOGIC; 
  signal N99_MC_D2_PT_10 : STD_LOGIC; 
  signal N99_MC_D2 : STD_LOGIC; 
  signal upper_enc_N162_MC_Q : STD_LOGIC; 
  signal upper_enc_N162_MC_D : STD_LOGIC; 
  signal upper_enc_N162_MC_D1 : STD_LOGIC; 
  signal data_trs_12_II_UIM : STD_LOGIC; 
  signal upper_enc_N162_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_N162_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_N162_MC_D2_PT_2 : STD_LOGIC; 
  signal data_trs_10_II_UIM : STD_LOGIC; 
  signal data_trs_11_II_UIM : STD_LOGIC; 
  signal data_trs_8_II_UIM : STD_LOGIC; 
  signal upper_enc_N162_MC_D2_PT_3 : STD_LOGIC; 
  signal data_trs_9_II_UIM : STD_LOGIC; 
  signal upper_enc_N162_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_enc_N162_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_enc_N162_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_enc_N162_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_enc_N162_MC_D2_PT_8 : STD_LOGIC; 
  signal upper_enc_N162_MC_D2 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_Q : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D1 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_8 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_9 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_10 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2_PT_11 : STD_LOGIC; 
  signal upper_enc_dis_func_N174_MC_D2 : STD_LOGIC; 
  signal N_PZ_328_MC_Q : STD_LOGIC; 
  signal N_PZ_328_MC_D : STD_LOGIC; 
  signal N_PZ_328_MC_D1 : STD_LOGIC; 
  signal N_PZ_328_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_328_MC_D2 : STD_LOGIC; 
  signal frame_out_enc_MC_Q : STD_LOGIC; 
  signal frame_out_enc_MC_D : STD_LOGIC; 
  signal frame_out_enc_MC_D1_PT_0 : STD_LOGIC; 
  signal frame_out_enc_MC_D1 : STD_LOGIC; 
  signal frame_out_enc_MC_D2 : STD_LOGIC; 
  signal serial_data_0_MC_Q : STD_LOGIC; 
  signal serial_data_0_MC_D : STD_LOGIC; 
  signal serial_data_0_MC_D1 : STD_LOGIC; 
  signal N_PZ_1744 : STD_LOGIC; 
  signal serial_data_0_MC_D2_PT_0 : STD_LOGIC; 
  signal serial_data_0_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_0_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_N164 : STD_LOGIC; 
  signal serial_data_0_MC_D2_PT_3 : STD_LOGIC; 
  signal serial_data_0_MC_D2 : STD_LOGIC; 
  signal N_PZ_1744_MC_Q : STD_LOGIC; 
  signal N_PZ_1744_MC_D : STD_LOGIC; 
  signal N_PZ_1744_MC_D1 : STD_LOGIC; 
  signal N_PZ_1744_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_1744_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_1744_MC_D2 : STD_LOGIC; 
  signal lower_enc_N164_MC_Q : STD_LOGIC; 
  signal lower_enc_N164_MC_D : STD_LOGIC; 
  signal FOOBAR2_ctinst_4 : STD_LOGIC; 
  signal lower_enc_N164_MC_D1 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_3 : STD_LOGIC; 
  signal N_PZ_1780 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_9 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_10 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_11 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_12 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_13 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_14 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_15 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2_PT_16 : STD_LOGIC; 
  signal lower_enc_N164_MC_D2 : STD_LOGIC; 
  signal N_PZ_1780_MC_Q : STD_LOGIC; 
  signal N_PZ_1780_MC_D : STD_LOGIC; 
  signal N_PZ_1780_MC_D1 : STD_LOGIC; 
  signal N_PZ_1780_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_1780_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_1780_MC_D2_PT_2 : STD_LOGIC; 
  signal N_PZ_1780_MC_D2 : STD_LOGIC; 
  signal serial_data_10_MC_Q : STD_LOGIC; 
  signal serial_data_10_MC_D : STD_LOGIC;