timesim.vhd

来自「以太网16B/20B源代码包括编码器和解码器功能」· VHDL 代码 · 共 1,107 行 · 第 1/5 页

  signal lower_enc_enc_8b_10b_c_prel_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_c_prel_MC_D2 : STD_LOGIC; 
  signal serial_data_8_MC_Q : STD_LOGIC; 
  signal serial_data_8_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel : STD_LOGIC; 
  signal serial_data_8_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_8_MC_D1 : STD_LOGIC; 
  signal serial_data_8_MC_D2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel_MC_Q : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel_MC_D1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_b_prel_MC_D2 : STD_LOGIC; 
  signal serial_data_9_MC_Q : STD_LOGIC; 
  signal serial_data_9_MC_D : STD_LOGIC; 
  signal serial_data_9_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_9_MC_D1 : STD_LOGIC; 
  signal serial_data_9_MC_D2 : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal NlwInverterSignal_FOOBAR4_ctinst_7_OUT : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_6_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_6_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_7_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_7_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_7_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_8_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_8_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_9_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_11_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_11_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_12_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_12_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_13_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_D2_PT_13_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_dis_out_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_4_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_5_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_5_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_6_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_6_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_7_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_7_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_7_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_8_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N160_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT3_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT3_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT3_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT3_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT3_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT3_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT1_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT1_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_prs_state_FFT2_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N98_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_dis_func_prs_state_FFD1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_dis_func_prs_state_FFD1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_dis_func_prs_state_FFD1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_prs_state_FFT1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_prs_state_FFT1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_prs_state_FFT1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_prs_state_FFT2_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_prs_state_FFT2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_prs_state_FFT2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_enc_8b_10b_prs_state_FFT2_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD2_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD2_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD2_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD2_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD2_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_s_func_prs_state_FFD2_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_prs_state_FFT1_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_prs_state_FFT1_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_prs_state_FFT1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_prs_state_FFT2_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_prs_state_FFT2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_prs_state_FFT2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_2_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_enc_8b_10b_prs_state_FFT2_MC_D1_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD1_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD1_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD1_MC_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_0_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_0_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_1_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_1_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_s_func_prs_state_FFD2_MC_D2_PT_2_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_5_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_6_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_7_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_8_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_9_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_10_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_11_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_12_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_13_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_14_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_15_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_dis_func_N132_MC_D2_PT_16_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_1737_MC_D1_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_1737_MC_D1_PT_0_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_1737_MC_XOR_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_3_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_4_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_4_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_lower_enc_N168_MC_D2_PT_4_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_330_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_330_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_330_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N_PZ_330_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_2_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_3_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_4_IN5 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_5_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_6_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_6_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_6_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_7_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_8_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_8_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_8_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_9_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_10_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_10_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_N99_MC_D2_PT_10_IN4 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_0_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_1_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_2_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_2_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_3_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_3_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_3_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_upper_enc_N162_MC_D2_PT_4_IN1 : STD_LOGIC;