timesim.vhd

来自「以太网16B/20B源代码包括编码器和解码器功能」· VHDL 代码 · 共 1,107 行 · 第 1/5 页

  signal FOOBAR5_ctinst_4 : STD_LOGIC; 
  signal serial_data_10_MC_D1 : STD_LOGIC; 
  signal N_PZ_1750 : STD_LOGIC; 
  signal serial_data_10_MC_D2_PT_0 : STD_LOGIC; 
  signal serial_data_10_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_10_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_N166 : STD_LOGIC; 
  signal serial_data_10_MC_D2_PT_3 : STD_LOGIC; 
  signal serial_data_10_MC_D2 : STD_LOGIC; 
  signal N_PZ_1750_MC_Q : STD_LOGIC; 
  signal N_PZ_1750_MC_D : STD_LOGIC; 
  signal N_PZ_1750_MC_D1 : STD_LOGIC; 
  signal N_PZ_1750_MC_D2_PT_0 : STD_LOGIC; 
  signal N_PZ_1750_MC_D2_PT_1 : STD_LOGIC; 
  signal N_PZ_1750_MC_D2 : STD_LOGIC; 
  signal upper_enc_N166_MC_Q : STD_LOGIC; 
  signal upper_enc_N166_MC_D : STD_LOGIC; 
  signal upper_enc_N166_MC_D1 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2_PT_8 : STD_LOGIC; 
  signal upper_enc_N166_MC_D2 : STD_LOGIC; 
  signal serial_data_11_MC_Q : STD_LOGIC; 
  signal serial_data_11_MC_D : STD_LOGIC; 
  signal serial_data_11_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_11_MC_D1 : STD_LOGIC; 
  signal serial_data_11_MC_D2 : STD_LOGIC; 
  signal serial_data_12_MC_Q : STD_LOGIC; 
  signal serial_data_12_MC_D : STD_LOGIC; 
  signal serial_data_12_MC_D1 : STD_LOGIC; 
  signal serial_data_12_MC_D2_PT_0 : STD_LOGIC; 
  signal serial_data_12_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_12_MC_D2_PT_2 : STD_LOGIC; 
  signal serial_data_12_MC_D2 : STD_LOGIC; 
  signal serial_data_13_MC_Q : STD_LOGIC; 
  signal serial_data_13_MC_D : STD_LOGIC; 
  signal serial_data_13_MC_D1 : STD_LOGIC; 
  signal serial_data_13_MC_D2_PT_0 : STD_LOGIC; 
  signal serial_data_13_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_13_MC_D2_PT_2 : STD_LOGIC; 
  signal serial_data_13_MC_D2 : STD_LOGIC; 
  signal serial_data_14_MC_Q : STD_LOGIC; 
  signal serial_data_14_MC_D : STD_LOGIC; 
  signal serial_data_14_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_14_MC_D1 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_0 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_2 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_3 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_4 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_5 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_6 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_7 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_8 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_9 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_10 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_11 : STD_LOGIC; 
  signal serial_data_14_MC_D2_PT_12 : STD_LOGIC; 
  signal serial_data_14_MC_D2 : STD_LOGIC; 
  signal serial_data_15_MC_Q : STD_LOGIC; 
  signal serial_data_15_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel : STD_LOGIC; 
  signal serial_data_15_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_15_MC_D1 : STD_LOGIC; 
  signal serial_data_15_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_Q : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D : STD_LOGIC; 
  signal FOOBAR3_ctinst_4 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_5 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_6 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_7 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_8 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_9 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_10 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2_PT_11 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_e_prel_MC_D2 : STD_LOGIC; 
  signal serial_data_16_MC_Q : STD_LOGIC; 
  signal serial_data_16_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel : STD_LOGIC; 
  signal serial_data_16_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_16_MC_D1 : STD_LOGIC; 
  signal serial_data_16_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel_MC_Q : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel_MC_D1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_d_prel_MC_D2 : STD_LOGIC; 
  signal serial_data_17_MC_Q : STD_LOGIC; 
  signal serial_data_17_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_c_prel : STD_LOGIC; 
  signal serial_data_17_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_17_MC_D1 : STD_LOGIC; 
  signal serial_data_17_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_c_prel_MC_Q : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_c_prel_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_c_prel_MC_D1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_c_prel_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_c_prel_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_c_prel_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_c_prel_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_c_prel_MC_D2 : STD_LOGIC; 
  signal serial_data_18_MC_Q : STD_LOGIC; 
  signal serial_data_18_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel : STD_LOGIC; 
  signal serial_data_18_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_18_MC_D1 : STD_LOGIC; 
  signal serial_data_18_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel_MC_Q : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel_MC_D1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel_MC_D2_PT_3 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel_MC_D2_PT_4 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_b_prel_MC_D2 : STD_LOGIC; 
  signal serial_data_19_MC_Q : STD_LOGIC; 
  signal serial_data_19_MC_D : STD_LOGIC; 
  signal serial_data_19_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_19_MC_D1 : STD_LOGIC; 
  signal serial_data_19_MC_D2 : STD_LOGIC; 
  signal serial_data_1_MC_Q : STD_LOGIC; 
  signal serial_data_1_MC_D : STD_LOGIC; 
  signal serial_data_1_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_1_MC_D1 : STD_LOGIC; 
  signal serial_data_1_MC_D2 : STD_LOGIC; 
  signal serial_data_2_MC_Q : STD_LOGIC; 
  signal serial_data_2_MC_D : STD_LOGIC; 
  signal serial_data_2_MC_D1 : STD_LOGIC; 
  signal serial_data_2_MC_D2_PT_0 : STD_LOGIC; 
  signal serial_data_2_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_2_MC_D2_PT_2 : STD_LOGIC; 
  signal serial_data_2_MC_D2 : STD_LOGIC; 
  signal serial_data_3_MC_Q : STD_LOGIC; 
  signal serial_data_3_MC_D : STD_LOGIC; 
  signal serial_data_3_MC_D1 : STD_LOGIC; 
  signal serial_data_3_MC_D2_PT_0 : STD_LOGIC; 
  signal serial_data_3_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_3_MC_D2_PT_2 : STD_LOGIC; 
  signal serial_data_3_MC_D2 : STD_LOGIC; 
  signal serial_data_4_MC_Q : STD_LOGIC; 
  signal serial_data_4_MC_D : STD_LOGIC; 
  signal serial_data_4_MC_D1 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_0 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_1 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_2 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_3 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_4 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_5 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_6 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_7 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_8 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_9 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_10 : STD_LOGIC; 
  signal serial_data_4_MC_D2_PT_11 : STD_LOGIC; 
  signal serial_data_4_MC_D2 : STD_LOGIC; 
  signal serial_data_5_MC_Q : STD_LOGIC; 
  signal serial_data_5_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel : STD_LOGIC; 
  signal serial_data_5_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_5_MC_D1 : STD_LOGIC; 
  signal serial_data_5_MC_D2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_Q : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D : STD_LOGIC; 
  signal FOOBAR1_ctinst_4 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_9 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_10 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2_PT_11 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_e_prel_MC_D2 : STD_LOGIC; 
  signal serial_data_6_MC_Q : STD_LOGIC; 
  signal serial_data_6_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel : STD_LOGIC; 
  signal serial_data_6_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_6_MC_D1 : STD_LOGIC; 
  signal serial_data_6_MC_D2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel_MC_Q : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel_MC_D1_PT_0 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel_MC_D1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_d_prel_MC_D2 : STD_LOGIC; 
  signal serial_data_7_MC_Q : STD_LOGIC; 
  signal serial_data_7_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_c_prel : STD_LOGIC; 
  signal serial_data_7_MC_D1_PT_0 : STD_LOGIC; 
  signal serial_data_7_MC_D1 : STD_LOGIC; 
  signal serial_data_7_MC_D2 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_c_prel_MC_Q : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_c_prel_MC_D : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_c_prel_MC_D1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_c_prel_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_c_prel_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_enc_8b_10b_c_prel_MC_D2_PT_2 : STD_LOGIC;