timesim.vhd

以太网16B/20B源代码包括编码器和解码器功能

-- Xilinx Vhdl produced by program ngd2vhdl E.30
-- Command: -rpw 100 -tpw 1 -ar Structure -xon true -w enc_16b20b.nga enc_16b20b_timesim.vhd 
-- Input file: enc_16b20b.nga
-- Output file: enc_16b20b_timesim.vhd
-- Design name: enc_16b20b
-- Xilinx: C:/Xilinx_WebPACK
-- # of Entities: 1
-- Device: XCR3128XL-6-VQ100

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized,
-- or used in any other manner other than simulation. This netlist uses simulation
-- primitives which may not represent the true implementation of the device, however
-- the netlist is functionally correct. Do not modify this file.

-- Model for  ROC (Reset-On-Configuration) Cell
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.VITAL_Timing.all;
entity ROC is
  generic (InstancePath: STRING := "*";
           WIDTH : Time := 100 ns);
  port(O : out std_ulogic := '1') ;
  attribute VITAL_LEVEL0 of ROC : entity is TRUE;
end ROC;

architecture ROC_V of ROC is
attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE;
begin
  ONE_SHOT : process
  begin
    if (WIDTH <= 0 ns) then
       assert FALSE report
       "*** Error: a positive value of WIDTH must be specified ***"
       severity failure;
    else
       wait for WIDTH;
       O <= '0';
    end if;
    wait;
  end process ONE_SHOT;
end ROC_V;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;
entity enc_16b20b is
  port (
    clk : in STD_LOGIC := 'X'; 
    dis_in : in STD_LOGIC := 'X'; 
    k_char : in STD_LOGIC := 'X'; 
    frame_in_enc : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    dis_out : out STD_LOGIC; 
    frame_out_enc : out STD_LOGIC; 
    data_trs : in STD_LOGIC_VECTOR ( 15 downto 0 ); 
    serial_data : out STD_LOGIC_VECTOR ( 19 downto 0 ) 
  );
end enc_16b20b;

architecture Structure of enc_16b20b is
  component ROC
    generic (InstancePath: STRING := "*";
             WIDTH : Time := 100 ns);
    port (O : out STD_ULOGIC := '1');
  end component;
  signal dis_out_MC_Q : STD_LOGIC; 
  signal dis_out_MC_D : STD_LOGIC; 
  signal clk_II_FCLK : STD_LOGIC; 
  signal FOOBAR4_ctinst_4 : STD_LOGIC; 
  signal rst_II_UIM : STD_LOGIC; 
  signal FOOBAR4_ctinst_7 : STD_LOGIC; 
  signal dis_out_MC_D1 : STD_LOGIC; 
  signal lower_enc_N160 : STD_LOGIC; 
  signal lower_enc_dis_func_N132 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3 : STD_LOGIC; 
  signal N_PZ_1737 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT2 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_3 : STD_LOGIC; 
  signal lower_enc_N168 : STD_LOGIC; 
  signal N_PZ_330 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_4 : STD_LOGIC; 
  signal N99 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_5 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_6 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_7 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_8 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_9 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_10 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_11 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_12 : STD_LOGIC; 
  signal dis_out_MC_D2_PT_13 : STD_LOGIC; 
  signal dis_out_MC_D2 : STD_LOGIC; 
  signal lower_enc_N160_MC_Q : STD_LOGIC; 
  signal lower_enc_N160_MC_D : STD_LOGIC; 
  signal lower_enc_N160_MC_D1 : STD_LOGIC; 
  signal data_trs_4_II_UIM : STD_LOGIC; 
  signal k_char_II_UIM : STD_LOGIC; 
  signal lower_enc_N160_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_N160_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT1 : STD_LOGIC; 
  signal lower_enc_prs_state_FFT2 : STD_LOGIC; 
  signal lower_enc_N160_MC_D2_PT_2 : STD_LOGIC; 
  signal data_trs_0_II_UIM : STD_LOGIC; 
  signal data_trs_1_II_UIM : STD_LOGIC; 
  signal data_trs_3_II_UIM : STD_LOGIC; 
  signal lower_enc_N160_MC_D2_PT_3 : STD_LOGIC; 
  signal data_trs_2_II_UIM : STD_LOGIC; 
  signal lower_enc_N160_MC_D2_PT_4 : STD_LOGIC; 
  signal lower_enc_N160_MC_D2_PT_5 : STD_LOGIC; 
  signal lower_enc_N160_MC_D2_PT_6 : STD_LOGIC; 
  signal lower_enc_N160_MC_D2_PT_7 : STD_LOGIC; 
  signal lower_enc_N160_MC_D2_PT_8 : STD_LOGIC; 
  signal lower_enc_N160_MC_D2 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3_MC_Q : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3_MC_D : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3_MC_D1 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3_MC_D2_PT_0 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3_MC_D2 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT3_MC_D_TFF : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1_MC_Q : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1_MC_D : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1_MC_D1 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1_MC_D2_PT_0 : STD_LOGIC; 
  signal N98 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1_MC_D2_PT_1 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1_MC_D2_PT_2 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1_MC_D2 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT1_MC_D_TFF : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT2_MC_Q : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT2_MC_R_OR_PRLD : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT2_MC_D : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT2_MC_D1_PT_0 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT2_MC_D1 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT2_MC_D2 : STD_LOGIC; 
  signal lower_enc_dis_func_prs_state_FFT2_MC_D_TFF : STD_LOGIC; 
  signal N98_MC_Q : STD_LOGIC; 
  signal N98_MC_R_OR_PRLD : STD_LOGIC; 
  signal N98_MC_D : STD_LOGIC; 
  signal N98_MC_D1 : STD_LOGIC; 
  signal upper_enc_dis_func_prs_state_FFD1 : STD_LOGIC; 
  signal N98_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_prs_state_FFT1 : STD_LOGIC; 
  signal upper_enc_prs_state_FFT2 : STD_LOGIC; 
  signal N98_MC_D2_PT_1 : STD_LOGIC; 
  signal N98_MC_D2 : STD_LOGIC; 
  signal upper_enc_dis_func_prs_state_FFD1_MC_Q : STD_LOGIC; 
  signal upper_enc_dis_func_prs_state_FFD1_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_dis_func_prs_state_FFD1_MC_D : STD_LOGIC; 
  signal upper_enc_dis_func_prs_state_FFD1_MC_D1 : STD_LOGIC; 
  signal upper_enc_dis_func_prs_state_FFD1_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_dis_func_prs_state_FFD1_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_dis_func_prs_state_FFD1_MC_D2 : STD_LOGIC; 
  signal upper_enc_dis_func_prs_state_FFD1_MC_D_TFF : STD_LOGIC; 
  signal upper_enc_prs_state_FFT1_MC_Q : STD_LOGIC; 
  signal upper_enc_prs_state_FFT1_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_prs_state_FFT1_MC_D : STD_LOGIC; 
  signal upper_enc_prs_state_FFT1_MC_D1 : STD_LOGIC; 
  signal frame_in_enc_II_UIM : STD_LOGIC; 
  signal upper_enc_prs_state_FFT1_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_prs_state_FFT1_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_prs_state_FFT1_MC_D2 : STD_LOGIC; 
  signal upper_enc_prs_state_FFT1_MC_D_TFF : STD_LOGIC; 
  signal upper_enc_prs_state_FFT2_MC_Q : STD_LOGIC; 
  signal upper_enc_prs_state_FFT2_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_prs_state_FFT2_MC_D : STD_LOGIC; 
  signal upper_enc_prs_state_FFT2_MC_D1 : STD_LOGIC; 
  signal upper_enc_prs_state_FFT2_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT2 : STD_LOGIC; 
  signal upper_enc_prs_state_FFT2_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_prs_state_FFT2_MC_D2 : STD_LOGIC; 
  signal upper_enc_prs_state_FFT2_MC_D_TFF : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3_MC_Q : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3_MC_D1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT3_MC_D_TFF : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1_MC_Q : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1_MC_D1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2_PT_2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT1_MC_D_TFF : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT2_MC_Q : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT2_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT2_MC_D : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT2_MC_D1_PT_0 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT2_MC_D1 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT2_MC_D2 : STD_LOGIC; 
  signal upper_enc_enc_8b_10b_prs_state_FFT2_MC_D_TFF : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD1_MC_Q : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD1_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD1_MC_D : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD1_MC_D1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD1_MC_D2_PT_0 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD1_MC_D2_PT_1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD1_MC_D2 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD2_MC_Q : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD2_MC_R_OR_PRLD : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD2_MC_D : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD2_MC_D1 : STD_LOGIC; 
  signal upper_enc_s_func_prs_state_FFD2_MC_D2_PT_0 : STD_LOGIC;