shiftreg.csf.qmsg

verilog实现shiftreg

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "0 " "Info: Fitter placement preparation operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACER_ESTIMATED_ROUTING_RESOURCE_USAGE" "" "Info: Design requires the following device routing resources:" { { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_COL_FSTTRK" "0 " "Info: Overall column FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_OVERALL_ROW_FSTTRK" "0 " "Info: Overall row FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_COL_FSTTRK" "0 " "Info: Maximum column FastTrack interconnect = 0%" {  } {  } 0} { "Info" "IFITAPI_FITAPI_INFO_VPR_ROUTING_RESOURCE_USAGE_MAX_ROW_FSTTRK" "1 " "Info: Maximum row FastTrack interconnect = 1%" {  } {  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "0.938 ns register register " "Info: Estimated most critical path is register to register delay of 0.938 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns Q\[3\]~reg0 1 REG LAB_2_A1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LAB_2_A1; Fanout = 2; REG Node = 'Q\[3\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { Q[3]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(0.531 ns) 0.938 ns Q\[2\]~reg0 2 REG LAB_2_A1 2 " "Info: 2: + IC(0.246 ns) + CELL(0.531 ns) = 0.938 ns; Loc. = LAB_2_A1; Fanout = 2; REG Node = 'Q\[2\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.777 ns" { Q[3]~reg0 Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.692 ns 73.77 % " "Info: Total cell delay = 0.692 ns ( 73.77 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.246 ns 26.23 % " "Info: Total interconnect delay = 0.246 ns ( 26.23 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.938 ns" { Q[3]~reg0 Q[2]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "0 " "Info: Fitter placement operations ending: elapsed time = 0 seconds" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "2 " "Info: Fitter routing operations ending: elapsed time = 2 seconds" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 13 16:27:38 2004 " "Info: Processing ended: Fri Aug 13 16:27:38 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Web Edition " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 13 16:28:06 2004 " "Info: Processing started: Fri Aug 13 16:28:06 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --lower_priority --import_settings_files=off --export_settings_files=off shiftreg -c shiftreg " "Info: Command: quartus_asm --lower_priority --import_settings_files=off --export_settings_files=off shiftreg -c shiftreg" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 13 16:28:13 2004 " "Info: Processing ended: Fri Aug 13 16:28:13 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}