shiftreg.tan.qmsg

verilog实现shiftreg

{ "Info" "ITDB_TSU_RESULT" "Q\[3\]~reg0 Di clk 4.211 ns register " "Info: tsu for register Q\[3\]~reg0 (data pin = Di, clock pin = clk) is 4.211 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.686 ns + Longest pin register " "Info: + Longest pin to register delay is 5.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns Di 1 PIN Pin_3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = Pin_3; Fanout = 1; PIN Node = 'Di'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { Di } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.367 ns) + CELL(0.079 ns) 5.686 ns Q\[3\]~reg0 2 REG LC5_2_A1 2 " "Info: 2: + IC(4.367 ns) + CELL(0.079 ns) = 5.686 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q\[3\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "4.446 ns" { Di Q[3]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns 23.20 % " "Info: Total cell delay = 1.319 ns ( 23.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.367 ns 76.80 % " "Info: Total interconnect delay = 4.367 ns ( 76.80 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "5.686 ns" { Di Q[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.673 ns - Shortest register " "Info: - Shortest clock path from clock clk to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK Pin_95 4 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns Q\[3\]~reg0 2 REG LC5_2_A1 2 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q\[3\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.783 ns" { clk Q[3]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.20 % " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns 46.80 % " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[3]~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "5.686 ns" { Di Q[3]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[3]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Q\[1\] Q\[1\]~reg0 5.713 ns register " "Info: tco from clock clk to destination pin Q\[1\] through register Q\[1\]~reg0 is 5.713 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.673 ns + Longest register " "Info: + Longest clock path from clock clk to source register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK Pin_95 4 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns Q\[1\]~reg0 2 REG LC6_2_A1 2 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC6_2_A1; Fanout = 2; REG Node = 'Q\[1\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.783 ns" { clk Q[1]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.20 % " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns 46.80 % " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[1]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.705 ns + Longest register pin " "Info: + Longest register to pin delay is 3.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns Q\[1\]~reg0 1 REG LC6_2_A1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC6_2_A1; Fanout = 2; REG Node = 'Q\[1\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { Q[1]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.054 ns) + CELL(2.490 ns) 3.705 ns Q\[1\] 2 PIN Pin_113 0 " "Info: 2: + IC(1.054 ns) + CELL(2.490 ns) = 3.705 ns; Loc. = Pin_113; Fanout = 0; PIN Node = 'Q\[1\]'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "3.544 ns" { Q[1]~reg0 Q[1] } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.651 ns 71.55 % " "Info: Total cell delay = 2.651 ns ( 71.55 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.054 ns 28.45 % " "Info: Total interconnect delay = 1.054 ns ( 28.45 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "3.705 ns" { Q[1]~reg0 Q[1] } "NODE_NAME" } } }  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[1]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "3.705 ns" { Q[1]~reg0 Q[1] } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Q\[3\]~reg0 Di clk -3.649 ns register " "Info: th for register Q\[3\]~reg0 (data pin = Di, clock pin = clk) is -3.649 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.673 ns + Longest register " "Info: + Longest clock path from clock clk to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK Pin_95 4 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns Q\[3\]~reg0 2 REG LC5_2_A1 2 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q\[3\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.783 ns" { clk Q[3]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.20 % " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns 46.80 % " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.364 ns + " "Info: + Micro hold delay of destination is 0.364 ns" {  } { { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.686 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.686 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns Di 1 PIN Pin_3 1 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = Pin_3; Fanout = 1; PIN Node = 'Di'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { Di } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.367 ns) + CELL(0.079 ns) 5.686 ns Q\[3\]~reg0 2 REG LC5_2_A1 2 " "Info: 2: + IC(4.367 ns) + CELL(0.079 ns) = 5.686 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q\[3\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "4.446 ns" { Di Q[3]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns 23.20 % " "Info: Total cell delay = 1.319 ns ( 23.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.367 ns 76.80 % " "Info: Total interconnect delay = 4.367 ns ( 76.80 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "5.686 ns" { Di Q[3]~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[3]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "5.686 ns" { Di Q[3]~reg0 } "NODE_NAME" } } }  } 0}
{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk Q\[2\] Q\[2\]~reg0 4.905 ns register " "Info: Minimum tco from clock clk to destination pin Q\[2\] through register Q\[2\]~reg0 is 4.905 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.673 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK Pin_95 4 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns Q\[2\]~reg0 2 REG LC3_2_A1 2 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC3_2_A1; Fanout = 2; REG Node = 'Q\[2\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.783 ns" { clk Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.20 % " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns 46.80 % " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.897 ns + Shortest register pin " "Info: + Shortest register to pin delay is 2.897 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns Q\[2\]~reg0 1 REG LC3_2_A1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC3_2_A1; Fanout = 2; REG Node = 'Q\[2\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.246 ns) + CELL(2.490 ns) 2.897 ns Q\[2\] 2 PIN Pin_110 0 " "Info: 2: + IC(0.246 ns) + CELL(2.490 ns) = 2.897 ns; Loc. = Pin_110; Fanout = 0; PIN Node = 'Q\[2\]'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "2.736 ns" { Q[2]~reg0 Q[2] } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.651 ns 91.51 % " "Info: Total cell delay = 2.651 ns ( 91.51 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.246 ns 8.49 % " "Info: Total interconnect delay = 0.246 ns ( 8.49 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "2.897 ns" { Q[2]~reg0 Q[2] } "NODE_NAME" } } }  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "2.897 ns" { Q[2]~reg0 Q[2] } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Aug 13 16:28:37 2004 " "Info: Processing ended: Fri Aug 13 16:28:37 2004" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}