shiftreg.tan.qmsg

verilog实现shiftreg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Web Edition " "Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Aug 13 16:28:35 2004 " "Info: Processing started: Fri Aug 13 16:28:35 2004" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --lower_priority --import_settings_files=off --export_settings_files=off shiftreg -c shiftreg " "Info: Command: quartus_tan --lower_priority --import_settings_files=off --export_settings_files=off shiftreg -c shiftreg" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTDB_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITDB_NODE_MAP_TO_CLK" "clk " "Info: Assuming node clk is an undefined clock" {  } { { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 2 -1 0 } } { "c:/quartus/bin/Assignment Editor.qase" "" "" { Assignment "c:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register Q\[3\]~reg0 Q\[2\]~reg0 290.02 MHz Internal " "Info: Clock clk Internal fmax is restricted to 290.02 MHz between source register Q\[3\]~reg0 and destination register Q\[2\]~reg0" { { "Info" "ITDB_CLOCK_RATE" "clock 3.448 ns " "Info: fmax restricted to clock pin edge rate 3.448 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.510 ns + Longest register register " "Info: + Longest register to register delay is 0.510 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns Q\[3\]~reg0 1 REG LC5_2_A1 2 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q\[3\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { Q[3]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.270 ns) + CELL(0.079 ns) 0.510 ns Q\[2\]~reg0 2 REG LC3_2_A1 2 " "Info: 2: + IC(0.270 ns) + CELL(0.079 ns) = 0.510 ns; Loc. = LC3_2_A1; Fanout = 2; REG Node = 'Q\[2\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.349 ns" { Q[3]~reg0 Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.240 ns 47.06 % " "Info: Total cell delay = 0.240 ns ( 47.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.270 ns 52.94 % " "Info: Total interconnect delay = 0.270 ns ( 52.94 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.510 ns" { Q[3]~reg0 Q[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 1.673 ns + Shortest register " "Info: + Shortest clock path from clock clk to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK Pin_95 4 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns Q\[2\]~reg0 2 REG LC3_2_A1 2 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC3_2_A1; Fanout = 2; REG Node = 'Q\[2\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.783 ns" { clk Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.20 % " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns 46.80 % " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[2]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 1.673 ns - Longest register " "Info: - Longest clock path from clock clk to source register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns clk 1 CLK Pin_95 4 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns Q\[3\]~reg0 2 REG LC5_2_A1 2 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q\[3\]~reg0'" {  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.783 ns" { clk Q[3]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns 53.20 % " "Info: Total cell delay = 0.890 ns ( 53.20 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns 46.80 % " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" {  } {  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[3]~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[3]~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" {  } { { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" {  } { { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "0.510 ns" { Q[3]~reg0 Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "1.673 ns" { clk Q[3]~reg0 } "NODE_NAME" } } }  } 0}  } { { "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" "" "" { Report "d:/lyp/shiftreg/db/shiftreg_cmp.qrpt" Compiler "shiftreg" "UNKNOWN" "V1" "d:/lyp/shiftreg/db/shiftreg.quartus_db" { Floorplan "" "" "" { Q[2]~reg0 } "NODE_NAME" } } } { "d:/lyp/shiftreg/shiftreg.v" "" "" { Text "d:/lyp/shiftreg/shiftreg.v" 12 -1 0 } }  } 0}