shiftreg.tan.rpt

verilog实现shiftreg

; N/A   ; None         ; 5.713 ns   ; Q[1]~reg0 ; Q[1] ; clk        ;
; N/A   ; None         ; 4.929 ns   ; Q[3]~reg0 ; Q[3] ; clk        ;
; N/A   ; None         ; 4.905 ns   ; Q[0]~reg0 ; Q[0] ; clk        ;
; N/A   ; None         ; 4.905 ns   ; Q[2]~reg0 ; Q[2] ; clk        ;
+-------+--------------+------------+-----------+------+------------+


+-----------------------------------------------------------------------+
; th                                                                    ;
+------------------------------------------------------------------------
; Minimum Slack ; Required th ; Actual th ; From ; To        ; To Clock ;
+---------------+-------------+-----------+------+-----------+----------+
; N/A           ; None        ; -3.649 ns ; Di   ; Q[3]~reg0 ; clk      ;
+---------------+-------------+-----------+------+-----------+----------+


+-----------------------------------------------------------------------------------+
; Minimum tco                                                                       ;
+------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From      ; To   ; From Clock ;
+---------------+------------------+----------------+-----------+------+------------+
; N/A           ; None             ; 4.905 ns       ; Q[2]~reg0 ; Q[2] ; clk        ;
; N/A           ; None             ; 4.905 ns       ; Q[0]~reg0 ; Q[0] ; clk        ;
; N/A           ; None             ; 4.929 ns       ; Q[3]~reg0 ; Q[3] ; clk        ;
; N/A           ; None             ; 5.713 ns       ; Q[1]~reg0 ; Q[1] ; clk        ;
+---------------+------------------+----------------+-----------+------+------------+


+---------------------------+
; Timing Analyzer Messages  ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.0 Build 214 3/25/2004 Service Pack 1 SJ Web Edition
    Info: Processing started: Fri Aug 13 16:28:35 2004
Info: Command: quartus_tan --lower_priority --import_settings_files=off --export_settings_files=off shiftreg -c shiftreg
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk Internal fmax is restricted to 290.02 MHz between source register Q[3]~reg0 and destination register Q[2]~reg0
    Info: fmax restricted to clock pin edge rate 3.448 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.510 ns
            Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q[3]~reg0'
            Info: 2: + IC(0.270 ns) + CELL(0.079 ns) = 0.510 ns; Loc. = LC3_2_A1; Fanout = 2; REG Node = 'Q[2]~reg0'
            Info: Total cell delay = 0.240 ns ( 47.06 % )
            Info: Total interconnect delay = 0.270 ns ( 52.94 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock clk to destination register is 1.673 ns
                Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC3_2_A1; Fanout = 2; REG Node = 'Q[2]~reg0'
                Info: Total cell delay = 0.890 ns ( 53.20 % )
                Info: Total interconnect delay = 0.783 ns ( 46.80 % )
            Info: - Longest clock path from clock clk to source register is 1.673 ns
                Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q[3]~reg0'
                Info: Total cell delay = 0.890 ns ( 53.20 % )
                Info: Total interconnect delay = 0.783 ns ( 46.80 % )
        Info: + Micro clock to output delay of source is 0.335 ns
        Info: + Micro setup delay of destination is 0.198 ns
Info: tsu for register Q[3]~reg0 (data pin = Di, clock pin = clk) is 4.211 ns
    Info: + Longest pin to register delay is 5.686 ns
        Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = Pin_3; Fanout = 1; PIN Node = 'Di'
        Info: 2: + IC(4.367 ns) + CELL(0.079 ns) = 5.686 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q[3]~reg0'
        Info: Total cell delay = 1.319 ns ( 23.20 % )
        Info: Total interconnect delay = 4.367 ns ( 76.80 % )
    Info: + Micro setup delay of destination is 0.198 ns
    Info: - Shortest clock path from clock clk to destination register is 1.673 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q[3]~reg0'
        Info: Total cell delay = 0.890 ns ( 53.20 % )
        Info: Total interconnect delay = 0.783 ns ( 46.80 % )
Info: tco from clock clk to destination pin Q[1] through register Q[1]~reg0 is 5.713 ns
    Info: + Longest clock path from clock clk to source register is 1.673 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC6_2_A1; Fanout = 2; REG Node = 'Q[1]~reg0'
        Info: Total cell delay = 0.890 ns ( 53.20 % )
        Info: Total interconnect delay = 0.783 ns ( 46.80 % )
    Info: + Micro clock to output delay of source is 0.335 ns
    Info: + Longest register to pin delay is 3.705 ns
        Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC6_2_A1; Fanout = 2; REG Node = 'Q[1]~reg0'
        Info: 2: + IC(1.054 ns) + CELL(2.490 ns) = 3.705 ns; Loc. = Pin_113; Fanout = 0; PIN Node = 'Q[1]'
        Info: Total cell delay = 2.651 ns ( 71.55 % )
        Info: Total interconnect delay = 1.054 ns ( 28.45 % )
Info: th for register Q[3]~reg0 (data pin = Di, clock pin = clk) is -3.649 ns
    Info: + Longest clock path from clock clk to destination register is 1.673 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q[3]~reg0'
        Info: Total cell delay = 0.890 ns ( 53.20 % )
        Info: Total interconnect delay = 0.783 ns ( 46.80 % )
    Info: + Micro hold delay of destination is 0.364 ns
    Info: - Shortest pin to register delay is 5.686 ns
        Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = Pin_3; Fanout = 1; PIN Node = 'Di'
        Info: 2: + IC(4.367 ns) + CELL(0.079 ns) = 5.686 ns; Loc. = LC5_2_A1; Fanout = 2; REG Node = 'Q[3]~reg0'
        Info: Total cell delay = 1.319 ns ( 23.20 % )
        Info: Total interconnect delay = 4.367 ns ( 76.80 % )
Info: Minimum tco from clock clk to destination pin Q[2] through register Q[2]~reg0 is 4.905 ns
    Info: + Shortest clock path from clock clk to source register is 1.673 ns
        Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = Pin_95; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC3_2_A1; Fanout = 2; REG Node = 'Q[2]~reg0'
        Info: Total cell delay = 0.890 ns ( 53.20 % )
        Info: Total interconnect delay = 0.783 ns ( 46.80 % )
    Info: + Micro clock to output delay of source is 0.335 ns
    Info: + Shortest register to pin delay is 2.897 ns
        Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC3_2_A1; Fanout = 2; REG Node = 'Q[2]~reg0'
        Info: 2: + IC(0.246 ns) + CELL(2.490 ns) = 2.897 ns; Loc. = Pin_110; Fanout = 0; PIN Node = 'Q[2]'
        Info: Total cell delay = 2.651 ns ( 91.51 % )
        Info: Total interconnect delay = 0.246 ns ( 8.49 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Aug 13 16:28:37 2004
    Info: Elapsed time: 00:00:02