shiftreg_2.v

verilog实现shiftreg

module shiftreg ( Di,clk,Q3,Q2,Q1,Q0);
input Di,clk;
output Q3,Q2,Q1,Q0;
reg Q3,Q2,Q1,Q0;

	always @(posedge clk)
	begin
		Q0 = Q1;
		Q1 = Q2;
		Q2 = Q3;
		Q3 = Di;
	end
endmodule