shiftreg_7.vhd

verilog实现shiftreg

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY altera;  USE altera.maxplus2.ALL;
ENTITY shiftreg IS
	GENERIC(width	: integer:=	4);
	PORT(Di,clk		 : IN	STD_LOGIC;
		 Q : OUT	STD_LOGIC_VECTOR(width-1 DOWNTO 0));
END shiftreg;
ARCHITECTURE a OF shiftreg IS
SIGNAL temp : STD_LOGIC_VECTOR(width-1 downto 1);
BEGIN
TOTAL:
FOR I IN Q'RANGE GENERATE
  START:
  IF (I = Q'high) GENERATE
	d3: dff 
	 PORT MAP (d => Di, clk => clk, clrn => '1', prn => '1', 
	           q => temp(width-1));
  END GENERATE;
  MIDDLE:
  IF (I < Q'high) AND (I > Q'low) GENERATE
	d2d1: dff 
	 PORT MAP (d => temp(I+1), clk => clk, clrn => '1', 
	           prn => '1',q => temp(I));
  END GENERATE;
  FINAL: 
  IF (I = Q'low) GENERATE
    d0: dff 
	 PORT MAP (d => temp(I+1), clk => clk, clrn => '1', 
	           prn => '1', q => Q(I));	
  END GENERATE;
END GENERATE;
Q(width-1 DOWNTO 1) <= temp;
END a;