shiftreg_1.vhd

verilog实现shiftreg

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY shiftreg IS
	PORT(Di,clk		 : IN	STD_LOGIC;
		 Q3,Q2,Q1,Q0 : OUT	STD_LOGIC);
END shiftreg;

ARCHITECTURE a OF shiftreg IS
	SIGNAL temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
 PROCESS (clk)
 BEGIN
	IF clk'event and clk = '1' THEN
        temp(3) <= Di;
        temp(2)<=temp(3);
        temp(1)<=temp(2);    
        temp(0)<=temp(1);
    END IF;
 END PROCESS;
END a;