phase_detector_top.tan.qmsg

使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。

{ "Info" "ITDB_TH_RESULT" "fq_divider:fq_divider_13_75m\|q rst clk_13_75m -2.318 ns register " "Info: th for register \"fq_divider:fq_divider_13_75m\|q\" (data pin = \"rst\", clock pin = \"clk_13_75m\") is -2.318 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_13_75m destination 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk_13_75m\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_13_75m 1 CLK PIN_14 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 12; CLK Node = 'clk_13_75m'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_13_75m } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns fq_divider:fq_divider_13_75m\|q 2 REG LC_X4_Y3_N6 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y3_N6; Fanout = 2; REG Node = 'fq_divider:fq_divider_13_75m\|q'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_13_75m fq_divider:fq_divider_13_75m|q } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_13_75m fq_divider:fq_divider_13_75m|q } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_13_75m clk_13_75m~combout fq_divider:fq_divider_13_75m|q } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 29 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.887 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.887 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_27 29 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 29; PIN Node = 'rst'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.512 ns) + CELL(1.243 ns) 5.887 ns fq_divider:fq_divider_13_75m\|q 2 REG LC_X4_Y3_N6 2 " "Info: 2: + IC(3.512 ns) + CELL(1.243 ns) = 5.887 ns; Loc. = LC_X4_Y3_N6; Fanout = 2; REG Node = 'fq_divider:fq_divider_13_75m\|q'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.755 ns" { rst fq_divider:fq_divider_13_75m|q } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.375 ns ( 40.34 % ) " "Info: Total cell delay = 2.375 ns ( 40.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.512 ns ( 59.66 % ) " "Info: Total interconnect delay = 3.512 ns ( 59.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.887 ns" { rst fq_divider:fq_divider_13_75m|q } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.887 ns" { rst rst~combout fq_divider:fq_divider_13_75m|q } { 0.000ns 0.000ns 3.512ns } { 0.000ns 1.132ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_13_75m fq_divider:fq_divider_13_75m|q } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_13_75m clk_13_75m~combout fq_divider:fq_divider_13_75m|q } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.887 ns" { rst fq_divider:fq_divider_13_75m|q } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.887 ns" { rst rst~combout fq_divider:fq_divider_13_75m|q } { 0.000ns 0.000ns 3.512ns } { 0.000ns 1.132ns 1.243ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 18 14:42:21 2007 " "Info: Processing ended: Mon Jun 18 14:42:21 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}