phase_detector_top.tan.qmsg

使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_13_75m register fq_divider:fq_divider_13_75m\|cnt\[4\] register fq_divider:fq_divider_13_75m\|cnt\[9\] 138.1 MHz 7.241 ns Internal " "Info: Clock \"clk_13_75m\" has Internal fmax of 138.1 MHz between source register \"fq_divider:fq_divider_13_75m\|cnt\[4\]\" and destination register \"fq_divider:fq_divider_13_75m\|cnt\[9\]\" (period= 7.241 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.532 ns + Longest register register " "Info: + Longest register to register delay is 6.532 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fq_divider:fq_divider_13_75m\|cnt\[4\] 1 REG LC_X5_Y3_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y3_N4; Fanout = 3; REG Node = 'fq_divider:fq_divider_13_75m\|cnt\[4\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { fq_divider:fq_divider_13_75m|cnt[4] } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.920 ns) + CELL(0.511 ns) 2.431 ns fq_divider:fq_divider_13_75m\|LessThan1~173 2 COMB LC_X4_Y3_N5 2 " "Info: 2: + IC(1.920 ns) + CELL(0.511 ns) = 2.431 ns; Loc. = LC_X4_Y3_N5; Fanout = 2; COMB Node = 'fq_divider:fq_divider_13_75m\|LessThan1~173'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.431 ns" { fq_divider:fq_divider_13_75m|cnt[4] fq_divider:fq_divider_13_75m|LessThan1~173 } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.511 ns) 3.704 ns fq_divider:fq_divider_13_75m\|LessThan1~174 3 COMB LC_X4_Y3_N0 10 " "Info: 3: + IC(0.762 ns) + CELL(0.511 ns) = 3.704 ns; Loc. = LC_X4_Y3_N0; Fanout = 10; COMB Node = 'fq_divider:fq_divider_13_75m\|LessThan1~174'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "1.273 ns" { fq_divider:fq_divider_13_75m|LessThan1~173 fq_divider:fq_divider_13_75m|LessThan1~174 } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.068 ns) + CELL(1.760 ns) 6.532 ns fq_divider:fq_divider_13_75m\|cnt\[9\] 4 REG LC_X5_Y3_N9 3 " "Info: 4: + IC(1.068 ns) + CELL(1.760 ns) = 6.532 ns; Loc. = LC_X5_Y3_N9; Fanout = 3; REG Node = 'fq_divider:fq_divider_13_75m\|cnt\[9\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.828 ns" { fq_divider:fq_divider_13_75m|LessThan1~174 fq_divider:fq_divider_13_75m|cnt[9] } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.782 ns ( 42.59 % ) " "Info: Total cell delay = 2.782 ns ( 42.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.750 ns ( 57.41 % ) " "Info: Total interconnect delay = 3.750 ns ( 57.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "6.532 ns" { fq_divider:fq_divider_13_75m|cnt[4] fq_divider:fq_divider_13_75m|LessThan1~173 fq_divider:fq_divider_13_75m|LessThan1~174 fq_divider:fq_divider_13_75m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "6.532 ns" { fq_divider:fq_divider_13_75m|cnt[4] fq_divider:fq_divider_13_75m|LessThan1~173 fq_divider:fq_divider_13_75m|LessThan1~174 fq_divider:fq_divider_13_75m|cnt[9] } { 0.000ns 1.920ns 0.762ns 1.068ns } { 0.000ns 0.511ns 0.511ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_13_75m destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_13_75m\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_13_75m 1 CLK PIN_14 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 12; CLK Node = 'clk_13_75m'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_13_75m } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns fq_divider:fq_divider_13_75m\|cnt\[9\] 2 REG LC_X5_Y3_N9 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N9; Fanout = 3; REG Node = 'fq_divider:fq_divider_13_75m\|cnt\[9\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_13_75m fq_divider:fq_divider_13_75m|cnt[9] } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_13_75m fq_divider:fq_divider_13_75m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_13_75m clk_13_75m~combout fq_divider:fq_divider_13_75m|cnt[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_13_75m source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk_13_75m\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_13_75m 1 CLK PIN_14 12 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_14; Fanout = 12; CLK Node = 'clk_13_75m'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_13_75m } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns fq_divider:fq_divider_13_75m\|cnt\[4\] 2 REG LC_X5_Y3_N4 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y3_N4; Fanout = 3; REG Node = 'fq_divider:fq_divider_13_75m\|cnt\[4\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_13_75m fq_divider:fq_divider_13_75m|cnt[4] } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_13_75m fq_divider:fq_divider_13_75m|cnt[4] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_13_75m clk_13_75m~combout fq_divider:fq_divider_13_75m|cnt[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_13_75m fq_divider:fq_divider_13_75m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_13_75m clk_13_75m~combout fq_divider:fq_divider_13_75m|cnt[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_13_75m fq_divider:fq_divider_13_75m|cnt[4] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_13_75m clk_13_75m~combout fq_divider:fq_divider_13_75m|cnt[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "6.532 ns" { fq_divider:fq_divider_13_75m|cnt[4] fq_divider:fq_divider_13_75m|LessThan1~173 fq_divider:fq_divider_13_75m|LessThan1~174 fq_divider:fq_divider_13_75m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "6.532 ns" { fq_divider:fq_divider_13_75m|cnt[4] fq_divider:fq_divider_13_75m|LessThan1~173 fq_divider:fq_divider_13_75m|LessThan1~174 fq_divider:fq_divider_13_75m|cnt[9] } { 0.000ns 1.920ns 0.762ns 1.068ns } { 0.000ns 0.511ns 0.511ns 1.760ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_13_75m fq_divider:fq_divider_13_75m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_13_75m clk_13_75m~combout fq_divider:fq_divider_13_75m|cnt[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_13_75m fq_divider:fq_divider_13_75m|cnt[4] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_13_75m clk_13_75m~combout fq_divider:fq_divider_13_75m|cnt[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "fq_divider:fq_divider_10m\|q rst clk_10m 3.240 ns register " "Info: tsu for register \"fq_divider:fq_divider_10m\|q\" (data pin = \"rst\", clock pin = \"clk_10m\") is 3.240 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.255 ns + Longest pin register " "Info: + Longest pin to register delay is 6.255 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_27 29 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 29; PIN Node = 'rst'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.880 ns) + CELL(1.243 ns) 6.255 ns fq_divider:fq_divider_10m\|q 2 REG LC_X4_Y4_N3 2 " "Info: 2: + IC(3.880 ns) + CELL(1.243 ns) = 6.255 ns; Loc. = LC_X4_Y4_N3; Fanout = 2; REG Node = 'fq_divider:fq_divider_10m\|q'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.123 ns" { rst fq_divider:fq_divider_10m|q } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.375 ns ( 37.97 % ) " "Info: Total cell delay = 2.375 ns ( 37.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.880 ns ( 62.03 % ) " "Info: Total interconnect delay = 3.880 ns ( 62.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "6.255 ns" { rst fq_divider:fq_divider_10m|q } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "6.255 ns" { rst rst~combout fq_divider:fq_divider_10m|q } { 0.000ns 0.000ns 3.880ns } { 0.000ns 1.132ns 1.243ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 29 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_10m destination 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_10m\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_10m 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk_10m'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_10m } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns fq_divider:fq_divider_10m\|q 2 REG LC_X4_Y4_N3 2 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N3; Fanout = 2; REG Node = 'fq_divider:fq_divider_10m\|q'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_10m fq_divider:fq_divider_10m|q } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m fq_divider:fq_divider_10m|q } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout fq_divider:fq_divider_10m|q } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "6.255 ns" { rst fq_divider:fq_divider_10m|q } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "6.255 ns" { rst rst~combout fq_divider:fq_divider_10m|q } { 0.000ns 0.000ns 3.880ns } { 0.000ns 1.132ns 1.243ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m fq_divider:fq_divider_10m|q } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout fq_divider:fq_divider_10m|q } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_10m out_d dff3 15.195 ns register " "Info: tco from clock \"clk_10m\" to destination pin \"out_d\" through register \"dff3\" is 15.195 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_10m source 3.348 ns + Longest register " "Info: + Longest clock path from clock \"clk_10m\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_10m 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk_10m'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_10m } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns dff3 2 REG LC_X4_Y4_N6 5 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N6; Fanout = 5; REG Node = 'dff3'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_10m dff3 } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m dff3 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout dff3 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 51 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.471 ns + Longest register pin " "Info: + Longest register to pin delay is 11.471 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dff3 1 REG LC_X4_Y4_N6 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N6; Fanout = 5; REG Node = 'dff3'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { dff3 } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(6.950 ns) 6.950 ns phase_detector:pha_dec\|nand9 2 COMB LOOP LC_X2_Y1_N3 2 " "Info: 2: + IC(0.000 ns) + CELL(6.950 ns) = 6.950 ns; Loc. = LC_X2_Y1_N3; Fanout = 2; COMB LOOP Node = 'phase_detector:pha_dec\|nand9'" { { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand7~76 LC_X2_Y1_N6 " "Info: Loc. = LC_X2_Y1_N6; Node \"phase_detector:pha_dec\|nand7~76\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand7~76 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand4 LC_X2_Y1_N4 " "Info: Loc. = LC_X2_Y1_N4; Node \"phase_detector:pha_dec\|nand4\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand4 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand9 LC_X2_Y1_N3 " "Info: Loc. = LC_X2_Y1_N3; Node \"phase_detector:pha_dec\|nand9\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand9 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand2 LC_X2_Y1_N2 " "Info: Loc. = LC_X2_Y1_N2; Node \"phase_detector:pha_dec\|nand2\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand2 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand8 LC_X2_Y1_N7 " "Info: Loc. = LC_X2_Y1_N7; Node \"phase_detector:pha_dec\|nand8\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand8 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand5 LC_X2_Y1_N5 " "Info: Loc. = LC_X2_Y1_N5; Node \"phase_detector:pha_dec\|nand5\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand7~76 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 21 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand4 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 18 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand9 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 23 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand2 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 16 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand8 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 22 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand5 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 19 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "6.950 ns" { dff3 phase_detector:pha_dec|nand9 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.199 ns) + CELL(2.322 ns) 11.471 ns out_d 3 PIN PIN_16 0 " "Info: 3: + IC(2.199 ns) + CELL(2.322 ns) = 11.471 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'out_d'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.521 ns" { phase_detector:pha_dec|nand9 out_d } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.272 ns ( 80.83 % ) " "Info: Total cell delay = 9.272 ns ( 80.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.199 ns ( 19.17 % ) " "Info: Total interconnect delay = 2.199 ns ( 19.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "11.471 ns" { dff3 phase_detector:pha_dec|nand9 out_d } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "11.471 ns" { dff3 phase_detector:pha_dec|nand9 out_d } { 0.000ns 0.000ns 2.199ns } { 0.000ns 6.950ns 2.322ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m dff3 } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout dff3 } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "11.471 ns" { dff3 phase_detector:pha_dec|nand9 out_d } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "11.471 ns" { dff3 phase_detector:pha_dec|nand9 out_d } { 0.000ns 0.000ns 2.199ns } { 0.000ns 6.950ns 2.322ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "rst fpga_rst 7.165 ns Longest " "Info: Longest tpd from source pin \"rst\" to destination pin \"fpga_rst\" is 7.165 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns rst 1 PIN PIN_27 29 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_27; Fanout = 29; PIN Node = 'rst'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.711 ns) + CELL(2.322 ns) 7.165 ns fpga_rst 2 PIN PIN_47 0 " "Info: 2: + IC(3.711 ns) + CELL(2.322 ns) = 7.165 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'fpga_rst'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "6.033 ns" { rst fpga_rst } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.454 ns ( 48.21 % ) " "Info: Total cell delay = 3.454 ns ( 48.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.711 ns ( 51.79 % ) " "Info: Total interconnect delay = 3.711 ns ( 51.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "7.165 ns" { rst fpga_rst } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "7.165 ns" { rst rst~combout fpga_rst } { 0.000ns 0.000ns 3.711ns } { 0.000ns 1.132ns 2.322ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}