phase_detector_top.tan.qmsg

使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "ITAN_SCC_LOOP" "6 " "Info: Found combinational loop of 6 nodes" { { "Info" "ITAN_SCC_NODE" "phase_detector:pha_dec\|nand5 " "Info: Node \"phase_detector:pha_dec\|nand5\"" {  } { { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 19 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Info" "ITAN_SCC_NODE" "phase_detector:pha_dec\|nand9 " "Info: Node \"phase_detector:pha_dec\|nand9\"" {  } { { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 23 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Info" "ITAN_SCC_NODE" "phase_detector:pha_dec\|nand4 " "Info: Node \"phase_detector:pha_dec\|nand4\"" {  } { { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 18 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Info" "ITAN_SCC_NODE" "phase_detector:pha_dec\|nand7~76 " "Info: Node \"phase_detector:pha_dec\|nand7~76\"" {  } { { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 21 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Info" "ITAN_SCC_NODE" "phase_detector:pha_dec\|nand2 " "Info: Node \"phase_detector:pha_dec\|nand2\"" {  } { { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 16 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0} { "Info" "ITAN_SCC_NODE" "phase_detector:pha_dec\|nand8 " "Info: Node \"phase_detector:pha_dec\|nand8\"" {  } { { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 22 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0}  } { { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 19 -1 0 } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 23 -1 0 } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 18 -1 0 } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 21 -1 0 } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 16 -1 0 } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 22 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_10m " "Info: Assuming node \"clk_10m\" is an undefined clock" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 23 -1 0 } } { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "clk_10m" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_13_75m " "Info: Assuming node \"clk_13_75m\" is an undefined clock" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 23 -1 0 } } { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "clk_13_75m" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_10m register fq_divider:fq_divider_10m\|cnt\[4\] register fq_divider:fq_divider_10m\|cnt\[9\] 152.51 MHz 6.557 ns Internal " "Info: Clock \"clk_10m\" has Internal fmax of 152.51 MHz between source register \"fq_divider:fq_divider_10m\|cnt\[4\]\" and destination register \"fq_divider:fq_divider_10m\|cnt\[9\]\" (period= 6.557 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.848 ns + Longest register register " "Info: + Longest register to register delay is 5.848 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fq_divider:fq_divider_10m\|cnt\[4\] 1 REG LC_X5_Y4_N4 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y4_N4; Fanout = 3; REG Node = 'fq_divider:fq_divider_10m\|cnt\[4\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { fq_divider:fq_divider_10m|cnt[4] } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.282 ns) + CELL(0.740 ns) 2.022 ns fq_divider:fq_divider_10m\|q~292 2 COMB LC_X4_Y4_N7 2 " "Info: 2: + IC(1.282 ns) + CELL(0.740 ns) = 2.022 ns; Loc. = LC_X4_Y4_N7; Fanout = 2; COMB Node = 'fq_divider:fq_divider_10m\|q~292'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.022 ns" { fq_divider:fq_divider_10m|cnt[4] fq_divider:fq_divider_10m|q~292 } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 2.527 ns fq_divider:fq_divider_10m\|LessThan1~116 3 COMB LC_X4_Y4_N8 2 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 2.527 ns; Loc. = LC_X4_Y4_N8; Fanout = 2; COMB Node = 'fq_divider:fq_divider_10m\|LessThan1~116'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "0.505 ns" { fq_divider:fq_divider_10m|q~292 fq_divider:fq_divider_10m|LessThan1~116 } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 3.032 ns fq_divider:fq_divider_10m\|cnt~195 4 COMB LC_X4_Y4_N9 10 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 3.032 ns; Loc. = LC_X4_Y4_N9; Fanout = 10; COMB Node = 'fq_divider:fq_divider_10m\|cnt~195'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "0.505 ns" { fq_divider:fq_divider_10m|LessThan1~116 fq_divider:fq_divider_10m|cnt~195 } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.056 ns) + CELL(1.760 ns) 5.848 ns fq_divider:fq_divider_10m\|cnt\[9\] 5 REG LC_X5_Y4_N9 3 " "Info: 5: + IC(1.056 ns) + CELL(1.760 ns) = 5.848 ns; Loc. = LC_X5_Y4_N9; Fanout = 3; REG Node = 'fq_divider:fq_divider_10m\|cnt\[9\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.816 ns" { fq_divider:fq_divider_10m|cnt~195 fq_divider:fq_divider_10m|cnt[9] } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.900 ns ( 49.59 % ) " "Info: Total cell delay = 2.900 ns ( 49.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.948 ns ( 50.41 % ) " "Info: Total interconnect delay = 2.948 ns ( 50.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.848 ns" { fq_divider:fq_divider_10m|cnt[4] fq_divider:fq_divider_10m|q~292 fq_divider:fq_divider_10m|LessThan1~116 fq_divider:fq_divider_10m|cnt~195 fq_divider:fq_divider_10m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.848 ns" { fq_divider:fq_divider_10m|cnt[4] fq_divider:fq_divider_10m|q~292 fq_divider:fq_divider_10m|LessThan1~116 fq_divider:fq_divider_10m|cnt~195 fq_divider:fq_divider_10m|cnt[9] } { 0.000ns 1.282ns 0.305ns 0.305ns 1.056ns } { 0.000ns 0.740ns 0.200ns 0.200ns 1.760ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_10m destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_10m\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_10m 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk_10m'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_10m } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns fq_divider:fq_divider_10m\|cnt\[9\] 2 REG LC_X5_Y4_N9 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N9; Fanout = 3; REG Node = 'fq_divider:fq_divider_10m\|cnt\[9\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_10m fq_divider:fq_divider_10m|cnt[9] } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m fq_divider:fq_divider_10m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout fq_divider:fq_divider_10m|cnt[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_10m source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk_10m\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk_10m 1 CLK PIN_12 16 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 16; CLK Node = 'clk_10m'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_10m } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns fq_divider:fq_divider_10m\|cnt\[4\] 2 REG LC_X5_Y4_N4 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X5_Y4_N4; Fanout = 3; REG Node = 'fq_divider:fq_divider_10m\|cnt\[4\]'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "2.185 ns" { clk_10m fq_divider:fq_divider_10m|cnt[4] } "NODE_NAME" } } { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m fq_divider:fq_divider_10m|cnt[4] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout fq_divider:fq_divider_10m|cnt[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m fq_divider:fq_divider_10m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout fq_divider:fq_divider_10m|cnt[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m fq_divider:fq_divider_10m|cnt[4] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout fq_divider:fq_divider_10m|cnt[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 53 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "5.848 ns" { fq_divider:fq_divider_10m|cnt[4] fq_divider:fq_divider_10m|q~292 fq_divider:fq_divider_10m|LessThan1~116 fq_divider:fq_divider_10m|cnt~195 fq_divider:fq_divider_10m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "5.848 ns" { fq_divider:fq_divider_10m|cnt[4] fq_divider:fq_divider_10m|q~292 fq_divider:fq_divider_10m|LessThan1~116 fq_divider:fq_divider_10m|cnt~195 fq_divider:fq_divider_10m|cnt[9] } { 0.000ns 1.282ns 0.305ns 0.305ns 1.056ns } { 0.000ns 0.740ns 0.200ns 0.200ns 1.760ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m fq_divider:fq_divider_10m|cnt[9] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout fq_divider:fq_divider_10m|cnt[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "3.348 ns" { clk_10m fq_divider:fq_divider_10m|cnt[4] } "NODE_NAME" } } { "d:/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus/win/Technology_Viewer.qrui" "3.348 ns" { clk_10m clk_10m~combout fq_divider:fq_divider_10m|cnt[4] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}