phase_detector_top.fit.qmsg

使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0 0 "Finished processing fast register assignments" 0 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "00:00:00 " "Extra Info: Finished moving registers into LUTs: elapsed time is 00:00:00" {  } {  } 1 0 "Finished moving registers into LUTs: elapsed time is %1!s!" 1 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" {  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Warning: Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "init_s " "Warning: Ignored I/O standard assignment to node \"init_s\"" {  } { { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "init_s" } } } }  } 0 0 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0}  } {  } 0 0 "Ignored I/O standard assignments to the following nodes" 0 0}
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Warning: Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "init_s " "Warning: Node \"init_s\" is assigned to location or region, but does not exist in design" {  } { { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "init_s" } } } }  } 0 0 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0}  } {  } 0 0 "Ignored locations or region assignments to the following nodes" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "11.058 ns register pin " "Info: Estimated most critical path is register to pin delay of 11.058 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dff3 1 REG LAB_X4_Y4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y4; Fanout = 5; REG Node = 'dff3'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { dff3 } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(7.050 ns) 7.050 ns phase_detector:pha_dec\|nand9 2 COMB LOOP LAB_X2_Y1 2 " "Info: 2: + IC(0.000 ns) + CELL(7.050 ns) = 7.050 ns; Loc. = LAB_X2_Y1; Fanout = 2; COMB LOOP Node = 'phase_detector:pha_dec\|nand9'" { { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand7~76 LAB_X2_Y1 " "Info: Loc. = LAB_X2_Y1; Node \"phase_detector:pha_dec\|nand7~76\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand7~76 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand4 LAB_X2_Y1 " "Info: Loc. = LAB_X2_Y1; Node \"phase_detector:pha_dec\|nand4\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand4 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand9 LAB_X2_Y1 " "Info: Loc. = LAB_X2_Y1; Node \"phase_detector:pha_dec\|nand9\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand9 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand8 LAB_X2_Y1 " "Info: Loc. = LAB_X2_Y1; Node \"phase_detector:pha_dec\|nand8\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand8 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand5 LAB_X2_Y1 " "Info: Loc. = LAB_X2_Y1; Node \"phase_detector:pha_dec\|nand5\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand5 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0} { "Info" "ITDB_PART_OF_SCC" "phase_detector:pha_dec\|nand2 LAB_X2_Y1 " "Info: Loc. = LAB_X2_Y1; Node \"phase_detector:pha_dec\|nand2\"" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand2 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand7~76 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 21 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand4 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 18 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand9 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 23 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand8 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 22 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand5 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 19 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { phase_detector:pha_dec|nand2 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 16 -1 0 } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "7.050 ns" { dff3 phase_detector:pha_dec|nand9 } "NODE_NAME" } } { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.686 ns) + CELL(2.322 ns) 11.058 ns out_d 3 PIN PIN_16 0 " "Info: 3: + IC(1.686 ns) + CELL(2.322 ns) = 11.058 ns; Loc. = PIN_16; Fanout = 0; PIN Node = 'out_d'" {  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "4.008 ns" { phase_detector:pha_dec|nand9 out_d } "NODE_NAME" } } { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.372 ns ( 84.75 % ) " "Info: Total cell delay = 9.372 ns ( 84.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.686 ns ( 15.25 % ) " "Info: Total interconnect delay = 1.686 ns ( 15.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "11.058 ns" { dff3 phase_detector:pha_dec|nand9 out_d } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "2 2 " "Info: Average interconnect usage is 2% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x0_y0 x8_y5 " "Info: The peak interconnect region extends from location x0_y0 to location x8_y5" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "5 " "Warning: Following 5 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "dpd GND " "Info: Pin dpd has GND driving its datain port" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 28 -1 0 } } { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "dpd" } } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { dpd } "NODE_NAME" } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { dpd } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "pll502\[0\] VCC " "Info: Pin pll502\[0\] has VCC driving its datain port" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 30 -1 0 } } { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "pll502\[0\]" } } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { pll502[0] } "NODE_NAME" } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { pll502[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "pll502\[1\] GND " "Info: Pin pll502\[1\] has GND driving its datain port" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 30 -1 0 } } { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "pll502\[1\]" } } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { pll502[1] } "NODE_NAME" } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { pll502[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "pll502\[2\] VCC " "Info: Pin pll502\[2\] has VCC driving its datain port" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 30 -1 0 } } { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "pll502\[2\]" } } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { pll502[2] } "NODE_NAME" } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { pll502[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "pll502\[3\] VCC " "Info: Pin pll502\[3\] has VCC driving its datain port" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 30 -1 0 } } { "d:/quartus/win/Assignment Editor.qase" "" { Assignment "d:/quartus/win/Assignment Editor.qase" 1 { { 0 "pll502\[3\]" } } } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { pll502[3] } "NODE_NAME" } } { "d:/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus/win/TimingClosureFloorplan.fld" "" "" { pll502[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 18 14:42:06 2007 " "Info: Processing ended: Mon Jun 18 14:42:06 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/phase_detector_top_v1.1/phase_detector_top.fit.smsg " "Info: Generated suppressed messages file F:/phase_detector_top_v1.1/phase_detector_top.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}