phase_detector_top.map.qmsg

使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 18 14:41:56 2007 " "Info: Processing started: Mon Jun 18 14:41:56 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off phase_detector_top -c phase_detector_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off phase_detector_top -c phase_detector_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fq_divider.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fq_divider.v" { { "Info" "ISGN_ENTITY_NAME" "1 fq_divider " "Info: Found entity 1: fq_divider" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 18 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "phase_detector.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file phase_detector.v" { { "Info" "ISGN_ENTITY_NAME" "1 phase_detector " "Info: Found entity 1: phase_detector" {  } { { "phase_detector.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "phase_detector_top.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file phase_detector_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 phase_detector_top " "Info: Found entity 1: phase_detector_top" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "phase_detector_top " "Info: Elaborating entity \"phase_detector_top\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fq_divider fq_divider:fq_divider_10m " "Info: Elaborating entity \"fq_divider\" for hierarchy \"fq_divider:fq_divider_10m\"" {  } { { "phase_detector_top.v" "fq_divider_10m" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 40 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 fq_divider.v(60) " "Warning (10230): Verilog HDL assignment warning at fq_divider.v(60): truncated value with size 32 to match size of target (10)" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 fq_divider.v(65) " "Warning (10230): Verilog HDL assignment warning at fq_divider.v(65): truncated value with size 32 to match size of target (10)" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fq_divider fq_divider:fq_divider_13_75m " "Info: Elaborating entity \"fq_divider\" for hierarchy \"fq_divider:fq_divider_13_75m\"" {  } { { "phase_detector_top.v" "fq_divider_13_75m" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 42 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 fq_divider.v(60) " "Warning (10230): Verilog HDL assignment warning at fq_divider.v(60): truncated value with size 32 to match size of target (10)" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 60 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 fq_divider.v(65) " "Warning (10230): Verilog HDL assignment warning at fq_divider.v(65): truncated value with size 32 to match size of target (10)" {  } { { "fq_divider.v" "" { Text "F:/phase_detector_top_v1.1/fq_divider.v" 65 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "phase_detector phase_detector:pha_dec " "Info: Elaborating entity \"phase_detector\" for hierarchy \"phase_detector:pha_dec\"" {  } { { "phase_detector_top.v" "pha_dec" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 46 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "ena fq_divider_13_75m 32 1 " "Warning: Port \"ena\" on the entity instantiation of \"fq_divider_13_75m\" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be driven by GND." {  } { { "phase_detector_top.v" "fq_divider_13_75m" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 42 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "ena fq_divider_10m 32 1 " "Warning: Port \"ena\" on the entity instantiation of \"fq_divider_10m\" is connected to a signal of width 32. The formal width of the signal in the module is 1.  Extra bits will be driven by GND." {  } { { "phase_detector_top.v" "fq_divider_10m" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 40 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "1 " "Info: Ignored 1 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "1 " "Info: Ignored 1 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "dpd GND " "Warning: Pin \"dpd\" stuck at GND" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 28 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pll502\[0\] VCC " "Warning: Pin \"pll502\[0\]\" stuck at VCC" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 30 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pll502\[1\] GND " "Warning: Pin \"pll502\[1\]\" stuck at GND" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 30 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pll502\[2\] VCC " "Warning: Pin \"pll502\[2\]\" stuck at VCC" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 30 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "pll502\[3\] VCC " "Warning: Pin \"pll502\[3\]\" stuck at VCC" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 30 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "oe " "Warning: No output dependent on input pin \"oe\"" {  } { { "phase_detector_top.v" "" { Text "F:/phase_detector_top_v1.1/phase_detector_top.v" 25 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "66 " "Info: Implemented 66 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "20 " "Info: Implemented 20 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "40 " "Info: Implemented 40 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 14 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 18 14:41:57 2007 " "Info: Processing ended: Mon Jun 18 14:41:57 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}