📄 phase_detector_top.map.rpt
字号:
; -- 0 input functions ; 0 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 22 ;
; -- arithmetic mode ; 18 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 20 ;
; -- asynchronous clear/load mode ; 20 ;
; ; ;
; Total registers ; 26 ;
; Total logic cells in carry chains ; 20 ;
; I/O pins ; 26 ;
; Maximum fan-out node ; rst ;
; Maximum fan-out ; 29 ;
; Total fan-out ; 183 ;
; Average fan-out ; 2.77 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-----------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+-----------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------+
; |phase_detector_top ; 40 (4) ; 26 ; 0 ; 26 ; 0 ; 14 (0) ; 4 (4) ; 22 (0) ; 20 (0) ; 0 (0) ; |phase_detector_top ;
; |fq_divider:fq_divider_10m| ; 16 (16) ; 11 ; 0 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 11 (11) ; 10 (10) ; 0 (0) ; |phase_detector_top|fq_divider:fq_divider_10m ;
; |fq_divider:fq_divider_13_75m| ; 14 (14) ; 11 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 11 (11) ; 10 (10) ; 0 (0) ; |phase_detector_top|fq_divider:fq_divider_13_75m ;
; |phase_detector:pha_dec| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |phase_detector_top|phase_detector:pha_dec ;
+-----------------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+--------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops ;
+--------------------------------------------------------+---+
; Logic Cell Name ; ;
+--------------------------------------------------------+---+
; phase_detector:pha_dec|out_u~0 ; ;
; phase_detector:pha_dec|nand5~0 ; ;
; phase_detector:pha_dec|nand6~0 ; ;
; phase_detector:pha_dec|nand3~0 ; ;
; Number of logic cells representing combinational loops ; 4 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 26 ;
; Number of registers using Synchronous Clear ; 20 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 20 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 2 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |phase_detector_top|fq_divider:fq_divider_10m|cnt[9] ;
; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |phase_detector_top|fq_divider:fq_divider_13_75m|cnt[9] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------------+
+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: fq_divider:fq_divider_10m ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+-----------------------------------------------+
; COUNTER ; 625 ; Integer ;
; width ; 10 ; Integer ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+---------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: fq_divider:fq_divider_13_75m ;
+----------------+-------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------------+
; COUNTER ; 1024 ; Integer ;
; width ; 10 ; Integer ;
+----------------+-------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Jun 18 14:41:56 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off phase_detector_top -c phase_detector_top
Info: Found 1 design units, including 1 entities, in source file fq_divider.v
Info: Found entity 1: fq_divider
Info: Found 1 design units, including 1 entities, in source file phase_detector.v
Info: Found entity 1: phase_detector
Info: Found 1 design units, including 1 entities, in source file phase_detector_top.v
Info: Found entity 1: phase_detector_top
Info: Elaborating entity "phase_detector_top" for the top level hierarchy
Info: Elaborating entity "fq_divider" for hierarchy "fq_divider:fq_divider_10m"
Warning (10230): Verilog HDL assignment warning at fq_divider.v(60): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at fq_divider.v(65): truncated value with size 32 to match size of target (10)
Info: Elaborating entity "fq_divider" for hierarchy "fq_divider:fq_divider_13_75m"
Warning (10230): Verilog HDL assignment warning at fq_divider.v(60): truncated value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at fq_divider.v(65): truncated value with size 32 to match size of target (10)
Info: Elaborating entity "phase_detector" for hierarchy "phase_detector:pha_dec"
Warning: Port "ena" on the entity instantiation of "fq_divider_13_75m" is connected to a signal of width 32. The formal width of the signal in the module is 1. Extra bits will be driven by GND.
Warning: Port "ena" on the entity instantiation of "fq_divider_10m" is connected to a signal of width 32. The formal width of the signal in the module is 1. Extra bits will be driven by GND.
Info: Ignored 1 buffer(s)
Info: Ignored 1 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
Warning: Pin "dpd" stuck at GND
Warning: Pin "pll502[0]" stuck at VCC
Warning: Pin "pll502[1]" stuck at GND
Warning: Pin "pll502[2]" stuck at VCC
Warning: Pin "pll502[3]" stuck at VCC
Warning: Design contains 1 input pin(s) that do not drive logic
Warning: No output dependent on input pin "oe"
Info: Implemented 66 device resources after synthesis - the final resource count might be different
Info: Implemented 6 input pins
Info: Implemented 20 output pins
Info: Implemented 40 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
Info: Processing ended: Mon Jun 18 14:41:57 2007
Info: Elapsed time: 00:00:02
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -