phase_detector_top.v

使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。

module phase_detector_top
	(
		clk_10m,
		clk_13_75m,
		txenable_in,
		adreset_fpga,
`unconnected_drive pull1
		oe,
		rst,
`nounconnected_drive
		out_u, 
		out_d,
//		init_s,
		//oe,
		txenable_out,
		dpd,
		adreset,
		clk_10m_out,
		pll502, dsp_nrst, brd_rst_led, aes_nrst, db_e1hrrst, svs_nrst, flash_nrst, fpga_rst,
		q_10m, q_13_75m, clk_13_75m_out
	);

	input clk_10m, clk_13_75m;
	input txenable_in, adreset_fpga;
	input oe, rst;
	output out_u, out_d;
	output txenable_out;
	output dpd, adreset;
	output clk_10m_out;
	output [3:0] pll502;
	output dsp_nrst, brd_rst_led, aes_nrst, db_e1hrrst, svs_nrst, flash_nrst, fpga_rst;
  	output q_10m, q_13_75m, clk_13_75m_out;

	reg sr1r, sr2r, sr1q, sr2q, sr1q_, sr2q_, intreg ;
	wire out_u, out_d;
	wire q_10m, q_13_75m, q_10m_int, q_13_75m_int, q_10m_reg, q_13_75m_reg;
//	parameter wait_width = 18;
//	reg [wait_width-1:0] q;
	
	fq_divider fq_divider_10m(.clk(clk_10m), .clrn(rst), .ena(1), .q(q_10m));
		defparam fq_divider_10m.COUNTER = 625;
	fq_divider fq_divider_13_75m(.clk(clk_13_75m), .clrn(rst), .ena(1), .q(q_13_75m));
		defparam fq_divider_13_75m.COUNTER = 1024;
//	lpm_counter wait_counter(.clock(clk_10m), .cnt_en(~q[wait_width-1]), .q(q), .aclr(~rst));
//		defparam wait_counter.lpm_width = wait_width;
	phase_detector pha_dec(.clka(q_10m_reg), .clkb(q_13_75m_reg), .out_u(out_u), .out_d(out_d));
	buf fan1(dsp_nrst, aes_nrst, svs_nrst, flash_nrst, fpga_rst, db_e1hrrst, rst);
//	buf fan2(brd_rst_led, adreset, ~rst);
	dff dff1(.d(q_10m), .clk(clk_10m), .q(q_10m_int));
	dff dff2(.d(q_13_75m), .clk(clk_10m), .q(q_13_75m_int));
	dff dff3(.d(q_10m_int), .clk(clk_10m), .q(q_10m_reg));
	dff dff4(.d(q_13_75m_int), .clk(clk_10m), .q(q_13_75m_reg));

	assign pll502 = 4'b1101;
//	assign aes_nrst = q[wait_width-1];
	assign txenable_out = txenable_in;
	assign dpd = 1'b0;
	//assign oe=1;
	assign adreset = adreset_fpga;
	assign clk_10m_out = clk_10m;
//	assign dsp_nrst = rst;
	assign brd_rst_led = ~rst;
//	assign aes_nrst = rst;
//	assign db_e1hrrst = ~rst;
//	assign svs_nrst = rst;
//	assign flash_nrst = rst;
	assign clk_13_75m_out = clk_13_75m;
//	assign fpga_rst = rst;
endmodule