phase_detector_top.fit.rpt

使用virlog语言编写的一个 锁相环的程序。可直接在cpld中应用。

; 4                                           ; 0                           ;
; 5                                           ; 0                           ;
; 6                                           ; 0                           ;
; 7                                           ; 0                           ;
; 8                                           ; 0                           ;
; 9                                           ; 0                           ;
; 10                                          ; 0                           ;
; 11                                          ; 0                           ;
; 12                                          ; 2                           ;
+---------------------------------------------+-----------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                        ;
+--------------------------------------------------------------------------------+-------------+
; Name                                                                           ; Value       ;
+--------------------------------------------------------------------------------+-------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff          ;
; Mid Wire Use - Fit Attempt 1                                                   ; 7           ;
; Mid Slack - Fit Attempt 1                                                      ; -16803      ;
; Internal Atom Count - Fit Attempt 1                                            ; 40          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 40          ;
; LAB Count - Fit Attempt 1                                                      ; 5           ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.400       ;
; Inputs per LAB - Fit Attempt 1                                                 ; 5.200       ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.400       ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:5         ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:3;1:2     ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:1;1:4     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:1;1:4     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:1;1:2;2:2 ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:1;1:2;2:2 ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:3;1:2     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:5         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:3;1:2     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 1:3;2:2     ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 1:4;2:1     ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:5         ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 1:5         ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:3;1:2     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:5         ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:5         ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:5         ;
; LEs in Chains - Fit Attempt 1                                                  ; 20          ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0           ;
; LABs with Chains - Fit Attempt 1                                               ; 2           ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0           ;
; Time - Fit Attempt 1                                                           ; 0           ;
+--------------------------------------------------------------------------------+-------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 2      ;
; Early Slack - Fit Attempt 1         ; -15197 ;
; Auto Fit Point 3 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 4      ;
; Mid Slack - Fit Attempt 1           ; -15197 ;
; Late Wire Use - Fit Attempt 1       ; 5      ;
; Late Slack - Fit Attempt 1          ; -15197 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.047  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -14596 ;
; Early Wire Use - Fit Attempt 1      ; 2      ;
; Peak Regional Wire - Fit Attempt 1  ; 2      ;
; Mid Slack - Fit Attempt 1           ; -14715 ;
; Late Slack - Fit Attempt 1          ; -14715 ;
; Late Slack - Fit Attempt 1          ; -14715 ;
; Late Wire Use - Fit Attempt 1       ; 5      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.063  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jun 18 14:42:02 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off phase_detector_top -c phase_detector_top
Info: Selected device EPM240T100C5 for design "phase_detector_top"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM240T100I5 is compatible
    Info: Device EPM570T100C5 is compatible
    Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted some destinations of signal "clk_10m" to use Global clock in PIN 12
    Info: Destination "clk_10m_out" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "clk_13_75m" to use Global clock in PIN 14
    Info: Destination "clk_13_75m_out" may be non-global or may not use global clock
Info: Automatically promoted some destinations of signal "rst" to use Global clock
    Info: Destination "brd_rst_led" may be non-global or may not use global clock
    Info: Destination "dsp_nrst" may be non-global or may not use global clock
    Info: Destination "db_e1hrrst" may be non-global or may