clk_div.v

VERILOG实现多时钟,可以应用于流水线.输入CLK,输出CLK1,CLK2,CLK3

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:21:07 10/29/2007 
// Design Name: 
// Module Name:    clk_div 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
module clk_div(//input
                clkin,
                //output
 					 clk1,clk2,clk3);
 input clkin;//定义输入端
 output clk1,clk2,clk3;//定义输出端口
 
 wire clkin,clk1,clk2,clk3;
 
 reg [2:0] step1=3'b000, step=3'b000;

 always @(posedge clkin)
   begin
     case (step)
      3'b001: step<=3'b010;
      3'b010: step<=3'b100;
      3'b100: step<=3'b001;
      default :step<=3'b001;
     endcase
   end

 always @(negedge clkin)
  begin
   case (step1)
      3'b001: step1<=3'b010;
      3'b010: step1<=3'b100;
      3'b100: step1<=3'b001;
      default :step1<=3'b001;
    endcase
  end

 assign clk1=step[0]&step1[0];
 assign clk2=step[1]&step1[1];
 assign clk3=step[2]&step1[2];

endmodule