dividefre.vhd

CPLD_EPM7064程序,运用计数器实现的分频程序,VHDL

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity dividefre is
  port(    input_high:in  std_logic;
          output_low1:out std_logic;
          output_low2:out std_logic;
          output_low3:out std_logic);
end dividefre;

architecture behavior of dividefre is
   signal output1:integer range 0 to 3999;
   signal output2:integer range 0 to 3767;
   signal output3:integer range 0 to 3555;
   signal output_1:std_logic;
   signal output_2:std_logic;
   signal output_3:std_logic;
     begin
     process(input_high)
       begin
       if(input_high'event and input_high='1') then
          if output3=3555 then
             output3<=0;
             output_3<='1';
          else output3<=output3+1;
             if output2=3767 then
                   output2<=0;
                   output_2<='1';
             else output2<=output2+1;
               if output1=3999 then
                   output_1<='1';
                   output1<=0;
               else output1<=output1+1;
               end if;        
             end if;
           end if;
        end if;
      end process;
   output_low3<=output_3;
   output_low2<=output_2;
   output_low1<=output_1;
    end behavior;