uart_115200.v

占用资源少的verilog HDL uart接口；采用固定波特率115200

module uart_115200	(
				sysclk,				
				tx_data,
				tx_wr,
				rx_rd,				
				rx,
				clr,
				
				tx,
				rx_data,
				tx_ready,
				rx_ready,
				buad_clk,
				tx_idle
			);

				input sysclk;				
				input[7:0]tx_data;
				input tx_wr;
				input rx_rd;
				input rx;
				input clr;
				
				output tx;
				output [7:0]rx_data;
				output tx_ready;
				output rx_ready;
				
				output buad_clk;
				output tx_idle;
				
				reg tx;
				reg [7:0]rx_data;
				reg rec_ready;
				
			/*get rx negedge to synchrony the buad clk*/			
			reg rx_delay;
			wire rx_posedge;
			always @(posedge sysclk)
				begin
					rx_delay<=rx;
				end
			assign rx_posedge=((~rx)& rx_delay);
			/*gerneral buad clk and receive tx data from cpu*/
			reg [7:0]tx_buff;
			reg tx_buff_full;
			reg tx_start_reg;
			wire tx_start;
			reg tx_idle;
			reg [10:0]buadcnt;
			reg buad_clk;
			
			always @(posedge sysclk or negedge clr)
				begin
				if(!clr)
					begin
						buadcnt<=0;
					end
				else
					begin						
						if(rx_posedge)
							begin							
							buad_clk<=0;
							buadcnt<=11'd426;
							end
						else if(buadcnt[10:0]==11'd853)
							begin
							buadcnt<=0;
							buad_clk<=1;							
							end
						else
							begin							
							buad_clk<=0;							
							buadcnt<=buadcnt+11'h1;					
							end
							
						if(tx_idle)
							begin								
							tx_buff_full<=0;
							end
						if(tx_wr)
							begin							
							tx_buff<=tx_data;
							tx_buff_full<=1;
							end
					end
				end
			assign tx_ready=tx_buff_full;
			assign tx_start=tx_start_reg;
			
			/*tx and rx entity*/
			reg head_in;
			reg [3:0]rec_bcnt;
			reg [3:0]trc_bcnt;
			reg [7:0]rec_buff;
			reg [7:0]trc_buff;
	
			always @(posedge sysclk or negedge clr)
				begin
				if(!clr)
					begin
					tx<=1;
					rx_data<=8'hff;
					rec_ready<=0;
					head_in<=0;
					rec_bcnt<=0;
					tx_idle<=0;
					end
				else
					begin
					if(buad_clk==1)
						begin
						if(rx==0)
							begin
								head_in<=1;
							end
						if(head_in==1)
							begin
							if(rec_bcnt[3:0]==4'h7)
								begin
								rec_bcnt<=0;
								head_in<=0;
								if(rx==1)
									begin
									rx_data<=rec_buff;
									rec_ready<=1;
									end
								end
							else
								begin
								rec_buff[7:1]<=rec_buff[6:0];
								rec_buff[0]<=rx;
								rec_bcnt<=rec_bcnt+4'h1;
								end
							end
						else
							begin
							rec_buff<=8'hff;
							rec_ready<=0;
							end
											
						
						if(trc_bcnt==4'h0)
							begin							
							if(tx_buff_full)
								begin
								tx<=0;
								tx_idle<=1;
								trc_bcnt<=4'h1;
								trc_buff<=tx_buff;								
								end
							else
								begin
								tx<=1;													
								tx_idle<=0;
								end
							end
						else if(trc_bcnt==4'h9)
							begin
							trc_bcnt<=0;
							tx<=1;
							end
						else
							begin
							tx_idle<=0;
							tx<=trc_buff[0];
							trc_buff[6:0]<=trc_buff[7:1];
							trc_bcnt<=trc_bcnt+4'h1;							
							end	
						end
					end				
				end
			assign rx_ready=rec_ready;
endmodule