clock.map.qmsg

verilog HDL综合实验源代码

{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(93) " "Warning: Verilog HDL assignment warning at clock.v(93): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 93 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(95) " "Warning: Verilog HDL assignment warning at clock.v(95): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 95 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(97) " "Warning: Verilog HDL assignment warning at clock.v(97): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 97 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(99) " "Warning: Verilog HDL assignment warning at clock.v(99): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 99 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(101) " "Warning: Verilog HDL assignment warning at clock.v(101): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 101 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(103) " "Warning: Verilog HDL assignment warning at clock.v(103): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 103 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(105) " "Warning: Verilog HDL assignment warning at clock.v(105): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 105 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(107) " "Warning: Verilog HDL assignment warning at clock.v(107): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 107 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(109) " "Warning: Verilog HDL assignment warning at clock.v(109): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 109 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clock.v(111) " "Warning: Verilog HDL assignment warning at clock.v(111): truncated value with size 32 to match size of target (4)" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 111 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dataout_buf\[2\] clock.v(74) " "Warning: Verilog HDL Always Construct warning at clock.v(74): variable \"dataout_buf\[2\]\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"dataout_buf\[2\]\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 74 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "dataout_buf\[5\] clock.v(74) " "Warning: Verilog HDL Always Construct warning at clock.v(74): variable \"dataout_buf\[5\]\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"dataout_buf\[5\]\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 74 0 0 } }  } 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "cnt_scan\[0\]~0 16 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=16) from the following logic: \"cnt_scan\[0\]~0\"" {  } { { "clock.v" "cnt_scan\[0\]~0" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 14 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 227 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "26 " "Info: Ignored 26 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "26 " "Info: Ignored 26 SOFT buffer(s)" {  } {  } 0}  } {  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 12 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 9 -1 0 } } { "clock.v" "" { Text "E:/Cindy/DevelopBoard/Mars-7128/示例程序/Verilog/综合实验/数字时钟/clock.v" 12 -1 0 } }  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin \"clk\" to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "rst " "Info: Promoted clear signal driven by pin \"rst\" to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "117 " "Info: Implemented 117 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "16 " "Info: Implemented 16 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "95 " "Info: Implemented 95 macrocells" {  } {  } 0} { "Info" "ISCL_SCL_TM_SEXPS" "4 " "Info: Implemented 4 shareable expanders" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 33 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 33 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 14 14:45:21 2005 " "Info: Processing ended: Wed Dec 14 14:45:21 2005" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:13 " "Info: Elapsed time: 00:00:13" {  } {  } 0}  } {  } 0}