traffic.map.summary

verilog HDL综合实验源代码

Flow Status : Successful - Wed Dec 14 14:42:50 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : traffic
Top-level Entity Name : traffic
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 74
Total pins : 15