key1.smp_dump.txt

来自「verilog HDL 接口试验源代码」· 文本 代码 · 共 20 行

State Machine - |key1|scan_key
Name scan_key~53 scan_key~52 scan_key~51 scan_key~50 
scan_key.0000 0 0 0 0 
scan_key.1110 0 0 1 0 
scan_key.1101 0 0 1 1 
scan_key.1100 0 1 1 0 
scan_key.1011 0 1 0 0 
scan_key.1010 0 1 0 1 
scan_key.1001 0 1 1 1 
scan_key.1000 1 0 0 0 
scan_key.0111 1 0 0 1 
scan_key.0110 1 0 1 0 
scan_key.0101 1 0 1 1 
scan_key.0100 1 1 0 0 
scan_key.0011 1 1 0 1 
scan_key.0010 1 1 1 0 
scan_key.0001 1 1 1 1 
scan_key.1111 0 0 0 1