mux.hier_info

来自「verilog HDL 基础实验源码」· HIER_INFO 代码 · 共 22 行

|mux
a => d_tmp[2].OUTPUTSELECT
a => d_tmp[1].OUTPUTSELECT
a => d_tmp[0].OUTPUTSELECT
b[0] => d_tmp[0].DATAB
b[1] => d_tmp[1].DATAB
b[2] => d_tmp[2].DATAB
c[0] => d_tmp[0].DATAA
c[1] => d_tmp[1].DATAA
c[2] => d_tmp[2].DATAA
d[0] <= <VCC>
d[1] <= d~6.DB_MAX_OUTPUT_PORT_TYPE
d[2] <= d~5.DB_MAX_OUTPUT_PORT_TYPE
d[3] <= d~4.DB_MAX_OUTPUT_PORT_TYPE
d[4] <= d~3.DB_MAX_OUTPUT_PORT_TYPE
d[5] <= d~2.DB_MAX_OUTPUT_PORT_TYPE
d[6] <= d~1.DB_MAX_OUTPUT_PORT_TYPE
d[7] <= d~0.DB_MAX_OUTPUT_PORT_TYPE
en <= <GND>