div.hier_info

verilog HDL 基础实验源码

|div
a[0] => LessThan~2.IN1
a[1] => LessThan~1.IN2
a[1] => add~1.IN2
a[1] => temp_reg~5.DATAA
a[2] => LessThan~0.IN3
a[2] => add~0.IN3
a[2] => temp_reg~3.DATAA
b[0] => reduce_nor~0.IN2
b[0] => LessThan~0.IN6
b[0] => temp_reg~2.IN0
b[0] => LessThan~1.IN5
b[0] => LessThan~2.IN4
b[1] => reduce_nor~0.IN1
b[1] => LessThan~0.IN5
b[1] => temp_reg~1.IN0
b[1] => LessThan~1.IN4
b[1] => LessThan~2.IN3
b[2] => reduce_nor~0.IN0
b[2] => LessThan~0.IN4
b[2] => temp_reg~0.IN0
b[2] => LessThan~1.IN3
b[2] => LessThan~2.IN2
c[0] <= <VCC>
c[1] <= c~6.DB_MAX_OUTPUT_PORT_TYPE
c[2] <= c~5.DB_MAX_OUTPUT_PORT_TYPE
c[3] <= c~4.DB_MAX_OUTPUT_PORT_TYPE
c[4] <= c~3.DB_MAX_OUTPUT_PORT_TYPE
c[5] <= c~2.DB_MAX_OUTPUT_PORT_TYPE
c[6] <= c~1.DB_MAX_OUTPUT_PORT_TYPE
c[7] <= c~0.DB_MAX_OUTPUT_PORT_TYPE
en[0] <= <GND>
en[1] <= <GND>
en[2] <= <GND>
en[3] <= <GND>
en[4] <= <GND>
en[5] <= <GND>
en[6] <= <GND>
en[7] <= <GND>