div.fit.summary

verilog HDL 基础实验源码

Flow Status : Successful - Wed Oct 12 10:17:30 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : div
Top-level Entity Name : div
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 19 / 128 ( 14 % )
Total pins : 26 / 68 ( 38 % )