threediv_clk.tan.qmsg

奇数分频和倍频

{ "Info" "ITDB_FULL_TCO_RESULT" "clk clkout clkout2~reg0 7.502 ns register " "Info: tco from clock \"clk\" to destination pin \"clkout\" through register \"clkout2~reg0\" is 7.502 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.630 ns) + CELL(0.542 ns) 3.000 ns clkout2~reg0 2 REG LC_X33_Y1_N2 4 " "Info: 2: + IC(1.630 ns) + CELL(0.542 ns) = 3.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 4; REG Node = 'clkout2~reg0'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "2.172 ns" { clk clkout2~reg0 } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.67 % ) " "Info: Total cell delay = 1.370 ns ( 45.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.630 ns ( 54.33 % ) " "Info: Total interconnect delay = 1.630 ns ( 54.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk clkout2~reg0 } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out0 clkout2~reg0 } { 0.000ns 0.000ns 1.630ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.346 ns + Longest register pin " "Info: + Longest register to pin delay is 4.346 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clkout2~reg0 1 REG LC_X33_Y1_N2 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 4; REG Node = 'clkout2~reg0'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "" { clkout2~reg0 } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.548 ns) + CELL(0.280 ns) 0.828 ns clkout~19 2 COMB LC_X33_Y1_N5 1 " "Info: 2: + IC(0.548 ns) + CELL(0.280 ns) = 0.828 ns; Loc. = LC_X33_Y1_N5; Fanout = 1; COMB Node = 'clkout~19'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "0.828 ns" { clkout2~reg0 clkout~19 } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(2.404 ns) 4.346 ns clkout 3 PIN PIN_P9 0 " "Info: 3: + IC(1.114 ns) + CELL(2.404 ns) = 4.346 ns; Loc. = PIN_P9; Fanout = 0; PIN Node = 'clkout'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "3.518 ns" { clkout~19 clkout } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.684 ns ( 61.76 % ) " "Info: Total cell delay = 2.684 ns ( 61.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.662 ns ( 38.24 % ) " "Info: Total interconnect delay = 1.662 ns ( 38.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "4.346 ns" { clkout2~reg0 clkout~19 clkout } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "4.346 ns" { clkout2~reg0 clkout~19 clkout } { 0.000ns 0.548ns 1.114ns } { 0.000ns 0.280ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk clkout2~reg0 } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out0 clkout2~reg0 } { 0.000ns 0.000ns 1.630ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "4.346 ns" { clkout2~reg0 clkout~19 clkout } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "4.346 ns" { clkout2~reg0 clkout~19 clkout } { 0.000ns 0.548ns 1.114ns } { 0.000ns 0.280ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "rst clkout 8.420 ns Longest " "Info: Longest tpd from source pin \"rst\" to destination pin \"clkout\" is 8.420 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns rst 1 PIN PIN_N8 5 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N8; Fanout = 5; PIN Node = 'rst'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.740 ns) + CELL(0.075 ns) 4.902 ns clkout~19 2 COMB LC_X33_Y1_N5 1 " "Info: 2: + IC(3.740 ns) + CELL(0.075 ns) = 4.902 ns; Loc. = LC_X33_Y1_N5; Fanout = 1; COMB Node = 'clkout~19'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "3.815 ns" { rst clkout~19 } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(2.404 ns) 8.420 ns clkout 3 PIN PIN_P9 0 " "Info: 3: + IC(1.114 ns) + CELL(2.404 ns) = 8.420 ns; Loc. = PIN_P9; Fanout = 0; PIN Node = 'clkout'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "3.518 ns" { clkout~19 clkout } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.566 ns ( 42.35 % ) " "Info: Total cell delay = 3.566 ns ( 42.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.854 ns ( 57.65 % ) " "Info: Total interconnect delay = 4.854 ns ( 57.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "8.420 ns" { rst clkout~19 clkout } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "8.420 ns" { rst rst~out0 clkout~19 clkout } { 0.000ns 0.000ns 3.740ns 1.114ns } { 0.000ns 1.087ns 0.075ns 2.404ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "clk1o rst clk -2.282 ns register " "Info: th for register \"clk1o\" (data pin = \"rst\", clock pin = \"clk\") is -2.282 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.000 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 4 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.630 ns) + CELL(0.542 ns) 3.000 ns clk1o 2 REG LC_X33_Y1_N7 1 " "Info: 2: + IC(1.630 ns) + CELL(0.542 ns) = 3.000 ns; Loc. = LC_X33_Y1_N7; Fanout = 1; REG Node = 'clk1o'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "2.172 ns" { clk clk1o } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.67 % ) " "Info: Total cell delay = 1.370 ns ( 45.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.630 ns ( 54.33 % ) " "Info: Total interconnect delay = 1.630 ns ( 54.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk clk1o } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out0 clk1o } { 0.000ns 0.000ns 1.630ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 5 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.382 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.382 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.087 ns) 1.087 ns rst 1 PIN PIN_N8 5 " "Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N8; Fanout = 5; PIN Node = 'rst'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.756 ns) + CELL(0.539 ns) 5.382 ns clk1o 2 REG LC_X33_Y1_N7 1 " "Info: 2: + IC(3.756 ns) + CELL(0.539 ns) = 5.382 ns; Loc. = LC_X33_Y1_N7; Fanout = 1; REG Node = 'clk1o'" {  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "4.295 ns" { rst clk1o } "NODE_NAME" } } { "threediv_clk.v" "" { Text "F:/a_panExmp/threediv_clk/threediv_clk.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.626 ns ( 30.21 % ) " "Info: Total cell delay = 1.626 ns ( 30.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.756 ns ( 69.79 % ) " "Info: Total interconnect delay = 3.756 ns ( 69.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "5.382 ns" { rst clk1o } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "5.382 ns" { rst rst~out0 clk1o } { 0.000ns 0.000ns 3.756ns } { 0.000ns 1.087ns 0.539ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "3.000 ns" { clk clk1o } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "3.000 ns" { clk clk~out0 clk1o } { 0.000ns 0.000ns 1.630ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus60/win/TimingClosureFloorplan.fld" "" "5.382 ns" { rst clk1o } "NODE_NAME" } } { "d:/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus60/win/Technology_Viewer.qrui" "5.382 ns" { rst rst~out0 clk1o } { 0.000ns 0.000ns 3.756ns } { 0.000ns 1.087ns 0.539ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Aug 29 16:41:45 2007 " "Info: Processing ended: Wed Aug 29 16:41:45 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}