threediv_clk.tan.rpt

奇数分频和倍频

+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 7.502 ns   ; clkout2~reg0 ; clkout  ; clk        ;
; N/A   ; None         ; 7.416 ns   ; clkout1~reg0 ; clkout  ; clk        ;
; N/A   ; None         ; 6.725 ns   ; clkout2~reg0 ; clkout2 ; clk        ;
; N/A   ; None         ; 6.724 ns   ; clkout1~reg0 ; clkout1 ; clk        ;
+-------+--------------+------------+--------------+---------+------------+


+-------------------------------------------------------------+
; tpd                                                         ;
+-------+-------------------+-----------------+------+--------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To     ;
+-------+-------------------+-----------------+------+--------+
; N/A   ; None              ; 8.420 ns        ; rst  ; clkout ;
+-------+-------------------+-----------------+------+--------+


+--------------------------------------------------------------------------+
; th                                                                       ;
+---------------+-------------+-----------+------+--------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To           ; To Clock ;
+---------------+-------------+-----------+------+--------------+----------+
; N/A           ; None        ; -2.282 ns ; rst  ; clk1o        ; clk      ;
; N/A           ; None        ; -2.287 ns ; rst  ; clkout1~reg0 ; clk      ;
; N/A           ; None        ; -2.287 ns ; rst  ; clk2o        ; clk      ;
; N/A           ; None        ; -2.288 ns ; rst  ; clkout2~reg0 ; clk      ;
+---------------+-------------+-----------+------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Wed Aug 29 16:41:45 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off threediv_clk -c threediv_clk --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 422.12 MHz between source register "clk1o" and destination register "clkout2~reg0"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.723 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y1_N7; Fanout = 1; REG Node = 'clk1o'
            Info: 2: + IC(0.404 ns) + CELL(0.319 ns) = 0.723 ns; Loc. = LC_X33_Y1_N2; Fanout = 4; REG Node = 'clkout2~reg0'
            Info: Total cell delay = 0.319 ns ( 44.12 % )
            Info: Total interconnect delay = 0.404 ns ( 55.88 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.000 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.630 ns) + CELL(0.542 ns) = 3.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 4; REG Node = 'clkout2~reg0'
                Info: Total cell delay = 1.370 ns ( 45.67 % )
                Info: Total interconnect delay = 1.630 ns ( 54.33 % )
            Info: - Longest clock path from clock "clk" to source register is 3.000 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
                Info: 2: + IC(1.630 ns) + CELL(0.542 ns) = 3.000 ns; Loc. = LC_X33_Y1_N7; Fanout = 1; REG Node = 'clk1o'
                Info: Total cell delay = 1.370 ns ( 45.67 % )
                Info: Total interconnect delay = 1.630 ns ( 54.33 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tsu for register "clkout2~reg0" (data pin = "rst", clock pin = "clk") is 2.398 ns
    Info: + Longest pin to register delay is 5.388 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N8; Fanout = 5; PIN Node = 'rst'
        Info: 2: + IC(3.762 ns) + CELL(0.539 ns) = 5.388 ns; Loc. = LC_X33_Y1_N2; Fanout = 4; REG Node = 'clkout2~reg0'
        Info: Total cell delay = 1.626 ns ( 30.18 % )
        Info: Total interconnect delay = 3.762 ns ( 69.82 % )
    Info: + Micro setup delay of destination is 0.010 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.630 ns) + CELL(0.542 ns) = 3.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 4; REG Node = 'clkout2~reg0'
        Info: Total cell delay = 1.370 ns ( 45.67 % )
        Info: Total interconnect delay = 1.630 ns ( 54.33 % )
Info: tco from clock "clk" to destination pin "clkout" through register "clkout2~reg0" is 7.502 ns
    Info: + Longest clock path from clock "clk" to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.630 ns) + CELL(0.542 ns) = 3.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 4; REG Node = 'clkout2~reg0'
        Info: Total cell delay = 1.370 ns ( 45.67 % )
        Info: Total interconnect delay = 1.630 ns ( 54.33 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 4.346 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 4; REG Node = 'clkout2~reg0'
        Info: 2: + IC(0.548 ns) + CELL(0.280 ns) = 0.828 ns; Loc. = LC_X33_Y1_N5; Fanout = 1; COMB Node = 'clkout~19'
        Info: 3: + IC(1.114 ns) + CELL(2.404 ns) = 4.346 ns; Loc. = PIN_P9; Fanout = 0; PIN Node = 'clkout'
        Info: Total cell delay = 2.684 ns ( 61.76 % )
        Info: Total interconnect delay = 1.662 ns ( 38.24 % )
Info: Longest tpd from source pin "rst" to destination pin "clkout" is 8.420 ns
    Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N8; Fanout = 5; PIN Node = 'rst'
    Info: 2: + IC(3.740 ns) + CELL(0.075 ns) = 4.902 ns; Loc. = LC_X33_Y1_N5; Fanout = 1; COMB Node = 'clkout~19'
    Info: 3: + IC(1.114 ns) + CELL(2.404 ns) = 8.420 ns; Loc. = PIN_P9; Fanout = 0; PIN Node = 'clkout'
    Info: Total cell delay = 3.566 ns ( 42.35 % )
    Info: Total interconnect delay = 4.854 ns ( 57.65 % )
Info: th for register "clk1o" (data pin = "rst", clock pin = "clk") is -2.282 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(1.630 ns) + CELL(0.542 ns) = 3.000 ns; Loc. = LC_X33_Y1_N7; Fanout = 1; REG Node = 'clk1o'
        Info: Total cell delay = 1.370 ns ( 45.67 % )
        Info: Total interconnect delay = 1.630 ns ( 54.33 % )
    Info: + Micro hold delay of destination is 0.100 ns
    Info: - Shortest pin to register delay is 5.382 ns
        Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_N8; Fanout = 5; PIN Node = 'rst'
        Info: 2: + IC(3.756 ns) + CELL(0.539 ns) = 5.382 ns; Loc. = LC_X33_Y1_N7; Fanout = 1; REG Node = 'clk1o'
        Info: Total cell delay = 1.626 ns ( 30.21 % )
        Info: Total interconnect delay = 3.756 ns ( 69.79 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Wed Aug 29 16:41:45 2007
    Info: Elapsed time: 00:00:03