fsm.v

it about using veriolog complement some project,thanks!

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test8
//filename    : file_fsm
//author      : wangyang
//data        : 2007/8/3
//version     : 1.0
//
//module name : module_fsm
//abstract     : use fsm design squence logic,
//               detctect squence"10010"
//
//modification history
//---------------------------------
//&Log&
//******************
module seqdet(X,Z,Clk,Rst,State);
input  X,Clk,Rst;
output Z;
output[2:0] State;
reg[2:0] State;
wire Z;


parameter IDLE='d0,  A='d1,  B='d2,
                     C='d3,  D='d4,
                     E='d5,  F='d6,
                     G='d7;
            
assign  Z = ( State==E && X==0 )? 1 : 0;  //?x=0???????E?
       //???D??x??1??????1????? State==E && X==0 ??
always @(posedge Clk)
   if(!Rst)
          begin
          State <= IDLE;
          end
   else
          case(State)
            IDLE : if(X==1)
                       begin  
                          State <= A;
                       end
            A:     if(X==0)
                       begin
                          State <= B;
                       end
            B:     if(X==0)
                       begin
                          State <= C;
                       end
                    else
                       begin
                          State <= F;
                       end
            C:      if(X==1)
                       begin
                          State <= D;
                       end
                    else
                       begin
                          State <= G;
                       end
            D:      if(X==0)
                       begin
                          State <= E;
                       end
                    else
                       begin
                          State <= A;
                       end
            E:      if(X==0)
                       begin
                          State <= C;
                       end
                    else
                       begin
                          State <= A;
                       end
            F:      if(X==1)
                       begin
                          State <= A;
                       end
                    else
                       begin
                          State <= B;
                       end
            G:      if(X==1)
                       begin
                          State <= F;
                       end
           default:State=IDLE;      //??????????
           endcase
endmodule


//???????
`timescale 1ns/1ns
//`include "./seqdet.v"
module seqdet_TEST;
  reg Clk,Rst;
  reg[23:0] Data;
  wire[2:0] State;
  wire Z,X;
  assign X=Data[23];
  always  #10 Clk = ~Clk;
  always @(posedge Clk)
         Data={Data[22:0],Data[23]};   //??????????
    //???????????????x?????????????
  initial
     begin
       Clk=0;
       Rst=1;
       #2 Rst=0;
       #30 Rst=1;
       Data ='b1100_1001_0000_1001_0100;
       #500 $stop;
     end
  
  seqdet  m(X,Z,Clk,Rst,State);
         
endmodule