half_clk_test.v

来自「it about using veriolog complement some 」· Verilog 代码 · 共 38 行

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test2
//filename    : file_half_clk_test
//author      : wangyang
//data        : 2007/8/2
//version     : 1.0
//
//module name : module_half_clk_test
//abstract     : half_clk_test
//
//modification history
//---------------------------------
//&Log&
//
//*************************
`timescale 1ns/100ps
`define clk_clycle 50
module half_clk_test;
reg Reset;
reg Clk_in;
wire Clk_out;

always #`clk_clycle Clk_in=~Clk_in;
initial
begin
Clk_in=0;
Reset=1;
#10 Reset=0;
#110 Reset=1;
#10000 $stop;
end

half_clk m(.Reset(Reset),.Clk_in(Clk_in),.Clk_out(Clk_out));
endmodule