compare.v

来自「it about using veriolog complement some 」· Verilog 代码 · 共 47 行

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test1
//filename    : compare
//author      : wangyang
//data        : 2007/8/2
//version     : 1.0
//
//module name : module_compare
//abstract     : if(a=b)=1,else0
//
//modification history
//---------------------------------
//&Log&
//
//*************************
module compare(A,B,Equal);
input A;
input B;
output Equal;
wire A;
wire B;
wire Equal;

assign Equal=(A==B)?1:0;//==???????=??????

endmodule

//??

/*module compare(A,B,Equal);
input A;
input B;
output Equal;
wire A;
wire B;
reg Equal;

always@(A or B)
if(A==B)
Equal=1;
else
Equal=0;
endmodule*/