compare_test.v

it about using veriolog complement some project,thanks!

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test1
//filename    : file_testbnech
//author      : wangyang
//data        : 2007/8/2
//version     : 1.0
//
//module name : module_compare_test
//abstract     : testbench
//
//modification history
//---------------------------------
//&Log&
//
//*************************
`timescale 1ns/1ns    //??????
`include"e:/verilog_study/compare.v"

module compare_test;
reg A,B;
wire Equal;
initial
begin
A=0;
B=0;
#100 A=0;B=1;
#100 A=1;B=1;
#100 A=1;B=0;
#100 A=0;B=0;
#100 $stop;
end

compare m(.A(A),.B(B),.Equal(Equal));
endmodule