function.v

来自「it about using veriolog complement some 」· Verilog 代码 · 共 79 行

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test6
//filename    : file_function
//author      : wangyang
//data        : 2007/8/2
//version     : 1.0
//
//module name : module_function
//abstract     : use function design ...
//
//modification history
//---------------------------------
//&Log&
//******************
module tryfunction(Clk,N,Result,Reset);
  input[3:0] N;
  input Reset;
  input Clk;
  output[31:0] Result;
  reg[31:0] Result;

  always @(posedge Clk)    //clk??????????
   begin
 		 if(!Reset)            //reset??????
    			Result<=0;
      	else
        		begin
          		Result <= N * Factorial(N)/((N*2)+1);
        		end
   end
  
  function [31:0] Factorial;      //?????
    input  [3:0]  Operand;
    reg    [3:0]  Index;
    begin
      Factorial = Operand ? 1 : 0;
      for(Index = 2; Index <= Operand; Index = Index + 1)
        Factorial = Index * Factorial;
    end
  endfunction
  
endmodule

//????????
//`include "./tryfunction.v"
`timescale 1ns/100ps
`define clk_cycle 50

module tryfuct_test;

reg[3:0] N,I;
reg Reset,Clk;

wire[31:0] Result;

initial
  begin
    N=0;
    Reset=1;
    Clk=0;
    #100 Reset=0;
    #100 Reset=1;
    for(I=0;I<=15;I=I+1)
      begin
        #200 N=I;
      end
    #100 $stop;
  end

always #`clk_cycle Clk=~Clk; 
 
tryfunction tryfunct(.Clk(Clk),.N(N),.Result(Result),.Reset(Reset));

endmodule