half_clk.v

it about using veriolog complement some project,thanks!

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test2
//filename    : file_half_clk
//author      : wangyang
//data        : 2007/8/2
//version     : 1.0
//
//module name : module_half_clk
//abstract     : half_clk
//
//modification history
//---------------------------------
//&Log&
//
//*************************
module half_clk(Reset,Clk_in,Clk_out);
input Reset;
input Clk_in;
output Clk_out;
wire Reset;
wire Clk_in;
reg Clk_out;

always@(posedge Clk_in)//???????????2??
begin:half_clk
if(!Reset) Clk_out=0;
else Clk_out=~Clk_out;
end
endmodule