blocking.v

it about using veriolog complement some project,thanks!

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test4
//filename    : file_blocking&unblocking
//author      : wangyang
//data        : 2007/8/2
//version     : 1.0
//
//module name : module_blocking
//abstract     : different of blocking&unblocking
//
//modification history
//---------------------------------
//&Log&
//
//*************************
// -------------   blocking.v ---------------

module blocking(Clk,A,B,C);
  output [3:0] B,C;
  input  [3:0] A;
  input        Clk;
  reg    [3:0] B,C;
  always @(posedge Clk)
   begin
    B = A;
    C = B;
    $display("Blocking: A = %d, B = %d, C = %d.",A,B,C); 
   end 
endmodule


//-------------  non_blocking.v -------------------
module non_blocking(Clk,A,B,C);

  output [3:0] B,C;
  input  [3:0] A;
  input        Clk;
  reg    [3:0] B,C;
  
  always @(posedge Clk)
  begin
    B <= A;
    C <= B;
    $display("Non_Blocking: A = %d, B = %d, C = %d.",A,B,C); 
  end
 
endmodule

//-------------  compareTop.v -----------------------------

`timescale 1ns/100ps
//`include "./blocking.v"
//`include "./non_blocking.v"

module compareTop;

  wire [3:0] b1,c1,b2,c2;
  reg  [3:0] a;
  reg  clk;
  
  initial
  begin
    clk = 0;
    forever #50 clk = ~clk;
  end
  
  initial
  
  begin
    a = 4'h3;
    $display("____________________________");
    # 100 a = 4'h7;
    $display("____________________________");
    # 100 a = 4'hf;
    $display("____________________________");
    # 100 a = 4'ha;
    $display("____________________________");
    # 100 a = 4'h2;
    $display("____________________________");
    # 100  $display("____________________________");
    $stop;
  end
  non_blocking  non_blocking(clk,a,b2,c2);
  blocking      blocking(clk,a,b1,c1);

endmodule