task.v

it about using veriolog complement some project,thanks!

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test7
//filename    : file_task
//author      : wangyang
//data        : 2007/8/2
//version     : 1.0
//
//module name : module_task
//abstract     : use task design ...
//
//modification history
//---------------------------------
//&Log&
//******************
module trytask(Ra,Rb,Rc,Rd,A,B,C,D);
  input[3:0] A,B,C,D;
  output[3:0] Ra,Rb,Rc,Rd;
  reg[3:0] Ra,Rb,Rc,Rd;
  reg[3:0] Va,Vb,Vc,Vd;
 
  always @ (A or B or C or D)
    begin
      {Va,Vb,Vc,Vd}={A,B,C,D};
      sort(Va,Vc);               //va ?vc???
      sort(Vb,Vd);               //vb ?vd???
      sort(Va,Vb);               //va ?vb???
      sort(Vc,Vd);               //vc ?vd???
      sort(Vb,Vc);               //vb ?vc???
      {Ra,Rb,Rc,Rd}={Va,Vb,Vc,Vd};
    end
    
  task sort;
    inout[3:0] X,Y;
    reg[3:0] Tmp;
    if(X>Y)
      begin
        Tmp=X;      //x?y??????????????????????????
        X=Y;
        Y=Tmp;
      end
  endtask

endmodule

//????

`timescale 1ns/100ps
//`include "task.v"

module task_test;
 reg[3:0]A,B,C,D;
 wire[3:0] Ra,Rb,Rc,Rd;

 initial
  begin
    A=0;B=0;C=0;D=0;
  repeat(5)
  begin 
      #100  A ={$random}%15;
            B ={$random}%15;  
            C ={$random}%15;
            D ={$random}%15;
  end
      
    #100 $stop;
end
    
trytask m(.Ra(Ra),.Rb(Rb),.Rc(Rc),.Rd(Rd),.A(A),.B(B),.C(C),.D(D));
             
endmodule