alu(use always).v

it about using veriolog complement some project,thanks!

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test5
//filename    : file_always_block
//author      : wangyang
//data        : 2007/8/2
//version     : 1.0
//
//module name : module_alu
//abstract     : use always_block design alu unit
//
//modification history
//---------------------------------
//&Log&
//******************
`define plus    3'd0 
`define minus   3'd1
`define band    3'd2
`define bor     3'd3
`define unegate 3'd4

module alu(Out,Opcode,A,B);
input[2:0] Opcode;
input[7:0] A;
input[7:0]B;              //???
output[7:0] Out;
reg[7:0]    Out;

always@(Opcode or A or B)    //?????always?
begin
      case(Opcode)
          `plus:  Out = A+B;   //????
          `minus: Out = A-B;  //????
          `band:  Out = A&B;   //???
          `bor:   Out = A|B;   //???
          `unegate:  Out=~A; //???
          default:   Out=8'hx;//?????????????
      endcase
end	
endmodule    

`timescale 1ns/1ns
//`include  "./alu.v"
module alu_test;
   wire[7:0] Out;
   reg[7:0]  A,B;
   reg[2:0]  Opcode;
   parameter   times=5;
   initial
    begin   
        A={$random}%256;  //Give a radom number blongs to [0,255] .
        B={$random}%256;  //Give a radom number blongs to [0,255].
        Opcode=3'h0;
        repeat(times)  //??5???????5???
          begin
          #100     A={$random}%256;  //Give a radom number.
                   B={$random}%256;  //Give a radom number.
                   Opcode=Opcode+1;
          end
                
        #100  $stop;
              
   end           

   alu    alu1(Out,Opcode,A,B);

endmodule