emob_module.v

it about using veriolog complement some project,thanks!

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test10
//filename    : file_module_emob
//author      : wangyang
//data        : 2007/8/3
//version     : 1.0
//
//module name : module_p_to_s
//abstract     : ???????
//
//modification history
//---------------------------------
//&Log&
//******************
module	p_to_s(D_in,T0,Data,SEND,ESC,ADD_100);
	input	[7:0] Data;               //????????
	input	      SEND,ESC,ADD_100;   //SEND?ESC???????????
                                      //??????ADD_100???????
	output	      D_in,T0;            // D_in??????T0???????
                                       // CPU???????????????
	wire	      D_in,T0;
	reg	[7:0] DATA_Q,DATA_Q_buf;

	assign	      T0 = ! (SEND & ESC);      //???????.
	assign	      D_in = DATA_Q[7];         //???????

	always @(posedge T0 or negedge ADD_100)  //ADD_100?????T0?????
	  begin
	    if(!ADD_100)
	      DATA_Q = Data;
	    else
	      begin
	      DATA_Q_buf = DATA_Q<<1;        //DATA_Q_buf??????????
	      DATA_Q	 = DATA_Q_buf;           //????
	      end
	  end

endmodule


module s_to_p(T1, Data, D_out,DSC,TAKE,ADD_101);
       output       T1;                     //?CPU??????CPU?????
                                            //????????              
       output [7:0] Data;                 
       input   D_out, DSC, TAKE, ADD_101;  //D_out?????????DSC?TAKE
                                           //?????????           
       wire   [7:0] Data;
       wire         T1,Clk2; 
       reg    [7:0] Data_latch, Data_latch_buf;
       
       assign       Clk2 = DSC  & TAKE ;   //???????       
       assign       T1 = !Clk2;
       
       assign       Data =  (!ADD_101) ? Data_latch : 8'bz;    
       always@(posedge Clk2)
            begin
               Data_latch_buf = Data_latch << 1;   //Data_latch_buf???
               Data_latch     = Data_latch_buf;   //??????????
                Data_latch[0] = D_out;
           end
endmodule


//`include "./p_to_s.v"
//`include "./s_to_p.v"
module sys(D_in,T0,T1, Data, D_out,SEND,ESC,DSC,TAKE,ADD_100,ADD_101);
  input         D_out,SEND,ESC,DSC,TAKE,ADD_100,ADD_101;
  inout  [7:0]  Data;
  output        D_in,T0,T1;
  
  p_to_s   p_to_s(.D_in(D_in),.T0(T0),.Data(Data),
                .SEND(SEND),.ESC(ESC),.ADD_100(ADD_100));
  s_to_p   s_to_p(.T1(T1),.Data(Data),.D_out(D_out),
          .DSC(DSC),.TAKE(TAKE),.ADD_101(ADD_101));
  
endmodule

//-------------Test file for sys.v ------------------
`timescale 1ns/100ps
//`include "./sys.v"
module TEST;
 reg D_out,SEND,ESC,DSC,TAKE,ADD_100,ADD_101;
 reg[7:0] Data_buf;
 wire [7:0] Data;
 wire Clk2;

 assign  Data = (ADD_101) ? Data_buf : 8'bz;   
                                 //data?sys??inout????ADD_101
                                 //??data????????????
assign  Clk2 =DSC && TAKE;

initial  
  begin
     SEND = 0;
     ESC = 0;
     DSC = 1;
     TAKE = 1;
     ADD_100 = 1;
     ADD_101 = 1;
  end

initial
  begin
    Data_buf = 8'b10000001;
    #90 ADD_100 = 0;
    #100 ADD_100 = 1;
  end

always 
  begin
    #50;
    SEND = ~SEND;
    ESC = ~ESC;
  end

initial
  begin
    #1500 ;
    SEND = 0;
    ESC  = 0;
    DSC  = 1;
    TAKE = 1;
    ADD_100 = 1;
    ADD_101 = 1;
    D_out = 0;    
    #1150 ADD_101 = 0;
    #100 ADD_101 =1;
    #100 $stop;
  end
  
always 
  begin
    #50 ;
    DSC = ~DSC;
    TAKE = ~TAKE;
  end
  
always @(negedge Clk2) D_out = ~D_out;

sys    sys(.D_in(D_in),.T0(T0),.T1(T1),.Data(Data),.D_out(D_out),
              .ADD_101(ADD_101), .SEND(SEND),.ESC(ESC),.DSC(DSC),
                                   .TAKE(TAKE),.ADD_100(ADD_100));  
endmodule