division.v

it about using veriolog complement some project,thanks!

//******************
//
//copyright 2007, DTK
//all right reserved
//
//project name: : test3
//filename    : file_division
//author      : wangyang
//data        : 2007/8/2
//version     : 1.0
//
//module name : module_division
//abstract     : squence_division
//
//modification history
//---------------------------------
//&Log&
//
//*************************
module division(Reset,F10MB,F500KB);
input Reset;
input F10MB;
output F500KB;
reg F500KB;
wire Reset;
wire F10MB;
reg [7:0] i;
always@(posedge F10MB)
if(!Reset)//?????
begin
    F500KB<=0;           
    i<=0;
end
else
begin
    if(i==9)//????????????F500KB??????
    begin
        i<=0;
        F500KB<=~F500KB;
    end
    else
    i<=i+1;
end
endmodule


`timescale 1ns/100ps
`define clk_cycle 50

module division_test;
reg F10MB;
reg Reset;
wire F500KB;
always #`clk_cycle F10MB=~F10MB;

initial
begin
Reset=1;
F10MB=0;
#100 Reset=0;
#100 Reset=1;
#10000 $stop;
end

division m(.Reset(Reset),.F10MB(F10MB),.F500KB(F500KB));
endmodule